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Date: Tue, 28 Nov 2017 15:04:17 +0100
From: Miquel RAYNAL <miquel.raynal@free-electrons.com>
To: Sean =?UTF-8?B?Tnlla2rDpnI=?= <sean.nyekjaer@prevas.dk>
Cc: ezequiel.garcia@free-electrons.com, linux-mtd@lists.infradead.org,
 "Kasper Revsbech (KREV)" <krev@triax.com>
Subject: Re: [BUG] pxa3xx: wait time out when scanning for bb
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Hi Sean,

> >> [=C2=A0=C2=A0=C2=A0 2.314939] pxa3xx-nand f10d0000.flash: ECC strength=
 16, ECC
> >> step size 2048 =20
> > In theory, Marvell NAND flash controller does support 16-bit
> > strength per 512 bytes over 2048 bytes pages. However, this
> > controller driver (pxa3xx_nand) does not. See [1] for the supported
> > configurations.
> >
> > The ECC strength shown here is probably the best to use with this
> > type of NAND device but I suggest you try with 4b/512B by using
> > these two properties like in [2]:
> >
> >          nand-ecc-strength =3D <4>;
> >          nand-ecc-step-size =3D <512>; =20
> My dts iscreated with great inspiration from the armada-385-dp-ap.dts
>=20
> &nand {
>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 status =3D "okay";
>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pinctrl-names =3D "default";
>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pinctrl-0 =3D <&nand_pins>, <=
&nand_rb>;
>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 num-cs =3D <1>;
>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 nand-on-flash-bbt;
>  =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 nand-ecc-strength =3D <4>;
>  =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0 nand-ecc-step-size =3D <512>;
> };

Just for testing purpose, could you also put the keep-config and
enable-arbiter properties ?

>=20
> Why does the driver not set these values?

Perhaps you can add traces there [3] and see where it fails?

[3]
http://elixir.free-electrons.com/linux/v4.14/source/drivers/mtd/nand/pxa3xx=
_nand.c#L1721

> (I only see the timeouts if I remove the nand-on-flash-bbt)

The nand-on-flash-bbt will read some of the last pages in you NAND chip
where a bad block table is supposed to be and derive from that
whether a block is bad or not. So this does only one read. I guess you
should have at least one timeout there?

Without this property, the NAND core will read every bad block marker
(a few bytes at the beginning of the OOB area) and detect if the block
was marked bad. Each access seems to produce a timeout, hence the big
amount of errors you see.

Thanks,
Miqu=C3=A8l