From: Miquel RAYNAL <miquel.raynal@free-electrons.com>
To: "Sean Nyekjær" <sean.nyekjaer@prevas.dk>
Cc: <ezequiel.garcia@free-electrons.com>,
<linux-mtd@lists.infradead.org>,
"Kasper Revsbech (KREV)" <krev@triax.com>,
Boris Brezillon <Boris.Brezillon@free-electrons.com>
Subject: Re: [BUG] pxa3xx: wait time out when scanning for bb
Date: Thu, 7 Dec 2017 21:38:14 +0100 [thread overview]
Message-ID: <20171207213814.4c57098f@xps13> (raw)
In-Reply-To: <744e99ee-91cf-28bc-21eb-c3fa01fb0a01@prevas.dk>
Hi Sean,
> > Can you add traces there [1] to see which path is used ?
> >
> > [1]
> > http://elixir.free-electrons.com/linux/latest/source/drivers/mtd/nand/pxa3xx_nand.c#L669
> >
> >
> I have inserted trace in drain_fifo:
> Line 672 right at the top
> Line 677 inside "if (info->ecc_bch)"
> Line 687 in the while loop
> Line 702 just before ioread32_rep
>
> [ 37.356209] pxa3xx-nand f10d0000.flash: pxa3xx_nand_irq():827
> nand_readl(0x0014) = 0x1
> [ 37.356214] pxa3xx-nand f10d0000.flash: pxa3xx_nand_irq():877
> nand_writel(0x1, 0x0014)
> [ 37.356219] pxa3xx-nand f10d0000.flash: pxa3xx_nand_irq():891
> nand_writel(0xd3000, 0x0048)
> [ 37.356224] pxa3xx-nand f10d0000.flash: pxa3xx_nand_irq():892
> nand_writel(0x2040000, 0x0048)
> [ 37.356228] pxa3xx-nand f10d0000.flash: pxa3xx_nand_irq():893
> nand_writel(0x0, 0x0048)
> [ 37.356233] pxa3xx-nand f10d0000.flash: pxa3xx_nand_irq():897
> nand_writel(0x0, 0x0048)
> [ 37.356256] pxa3xx-nand f10d0000.flash: pxa3xx_nand_irq():827
> nand_readl(0x0014) = 0x800
> [ 37.356261] pxa3xx-nand f10d0000.flash: pxa3xx_nand_irq():877
> nand_writel(0x800, 0x0014)
> [ 37.356376] pxa3xx-nand f10d0000.flash: pxa3xx_nand_irq():827
> nand_readl(0x0014) = 0x2
> [ 37.356386] pxa3xx-nand f10d0000.flash: drain_fifo():672
> [ 37.356390] pxa3xx-nand f10d0000.flash: drain_fifo():677
> [ 37.356394] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356400] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356405] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356410] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356415] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356420] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356425] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356430] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356435] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356440] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356446] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356451] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356456] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356461] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356466] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356471] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356476] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356481] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356486] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356491] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356497] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356502] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356507] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356512] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356517] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356522] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356527] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356532] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356537] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356542] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356548] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356553] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356558] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356563] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356568] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356573] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356578] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356583] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356588] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356593] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356598] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356604] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356609] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356614] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356619] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356624] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356629] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356634] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356639] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356644] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356650] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356655] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356660] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356665] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356670] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356675] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356680] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356685] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356690] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356695] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356700] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356705] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356711] pxa3xx-nand f10d0000.flash: drain_fifo():687
> [ 37.356716] pxa3xx-nand f10d0000.flash: drain_fifo():702
> [ 37.356721] pxa3xx-nand f10d0000.flash: drain_fifo():672
> [ 37.356725] pxa3xx-nand f10d0000.flash: drain_fifo():677
> [ 37.356728] pxa3xx-nand f10d0000.flash: drain_fifo():702
> [ 37.356734] pxa3xx-nand f10d0000.flash:
> pxa3xx_nand_irq_thread():807 nand_writel(0x6, 0x0014)
> [ 37.560189] pxa3xx-nand f10d0000.flash: Wait time out!!!
> [ 37.565521] pxa3xx-nand f10d0000.flash: pxa3xx_nand_stop():636
> nand_readl(0x0000) = 0x91078000
>
I had a look at the traces you provided, but I could not find a
plausible explanation for the timeouts.
As you may know, I am actively working on a new interface in the NAND
core called ->exec_op() (see [1] and [2]) and the first driver to
implement this interface is a rework of pxa3xx_nand.c renamed
marvell_nand.c (see [3]).
May I suggest you to test these changes and report me if it fails? I
prepared a branch ready to be tested (just add your own device tree),
available on my Github at [4].
If you have failures, it would be great to enable dynamic debug in the
core (put #define DEBUG before all #includes in
drivers/mtd/nand/nand_core.c) and report on the mailing list what you
get. Otherwise, you may stack this commits on top of your branch, or
wait for 4.16 to be released (hopefully).
Thanks,
Miquèl
[1] https://www.spinics.net/lists/arm-kernel/msg619633.html
[2] http://lists.infradead.org/pipermail/linux-mtd/2017-December/077965.html
[3] http://lists.infradead.org/pipermail/linux-mtd/2017-December/077973.html
[4] https://github.com/miquelraynal/linux/tree/marvell/nand-next/nfc-rework
next prev parent reply other threads:[~2017-12-07 20:38 UTC|newest]
Thread overview: 85+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-28 9:12 [BUG] pxa3xx: wait time out when scanning for bb Sean Nyekjær
2017-11-28 13:02 ` Miquel RAYNAL
2017-11-28 13:12 ` Sean Nyekjær
2017-11-28 13:30 ` Miquel RAYNAL
2017-11-28 13:42 ` Sean Nyekjær
2017-11-28 14:04 ` Miquel RAYNAL
2017-11-29 7:14 ` Sean Nyekjær
2017-11-29 8:03 ` Miquel RAYNAL
2017-11-30 12:00 ` Sean Nyekjær
2017-11-30 17:18 ` Miquel RAYNAL
2017-11-30 18:13 ` Sean Nyekjær
2017-12-01 8:15 ` Miquel RAYNAL
2017-12-01 8:54 ` Sean Nyekjær
2017-12-07 20:38 ` Miquel RAYNAL [this message]
2017-12-08 9:04 ` Sean Nyekjær
2017-12-08 9:21 ` Miquel RAYNAL
2017-12-11 8:25 ` Sean Nyekjær
2017-12-11 8:45 ` Sean Nyekjær
2017-12-11 9:53 ` Miquel RAYNAL
2017-12-11 10:20 ` Sean Nyekjær
2017-12-11 11:35 ` Sean Nyekjær
2017-12-11 13:22 ` Sean Nyekjær
2017-12-11 14:02 ` Miquel RAYNAL
2017-12-11 14:09 ` Miquel RAYNAL
2017-12-11 14:49 ` Boris Brezillon
2017-12-12 8:44 ` Sean Nyekjær
2017-12-12 8:51 ` Miquel RAYNAL
2017-12-12 8:56 ` Sean Nyekjær
2017-12-12 10:12 ` Miquel RAYNAL
2017-12-12 10:55 ` Sean Nyekjær
2017-12-12 11:08 ` Miquel RAYNAL
2017-12-12 11:28 ` Sean Nyekjær
2017-12-12 11:35 ` Miquel RAYNAL
2017-12-12 11:49 ` Sean Nyekjær
2017-12-12 12:47 ` Miquel RAYNAL
2017-12-12 13:09 ` Sean Nyekjær
2017-12-12 13:35 ` Miquel RAYNAL
2017-12-12 18:10 ` Sean Nyekjær
2017-12-12 18:23 ` Miquel RAYNAL
2017-12-13 6:25 ` Sean Nyekjær
2017-12-13 8:41 ` Miquel RAYNAL
2017-12-13 9:31 ` Sean Nyekjær
2017-12-15 17:25 ` Miquel RAYNAL
2017-12-15 18:56 ` Sean Nyekjær
2017-12-15 19:19 ` Miquel RAYNAL
2017-12-17 11:56 ` Sean Nyekjaer
2017-12-17 13:19 ` Boris Brezillon
2017-12-17 21:47 ` Sean Nyekjaer
2017-12-17 22:00 ` Boris Brezillon
2017-12-17 22:15 ` [SPAM] " Sean Nyekjær
2017-12-17 22:19 ` Boris Brezillon
2017-12-17 22:19 ` Miquel RAYNAL
2017-12-18 6:23 ` Sean Nyekjær
2017-12-18 8:56 ` Miquel RAYNAL
2017-12-18 9:26 ` Sean Nyekjær
2017-12-18 9:35 ` Miquel RAYNAL
2017-12-18 10:12 ` Sean Nyekjær
2017-12-18 10:19 ` Miquel RAYNAL
2017-12-18 10:26 ` Sean Nyekjær
2017-12-18 10:45 ` Boris Brezillon
2017-12-18 10:48 ` Sean Nyekjær
2017-12-18 12:43 ` Boris Brezillon
2017-12-18 8:57 ` [SPAM] " Boris Brezillon
2017-12-17 13:48 ` Boris Brezillon
2017-12-11 20:11 ` Miquel RAYNAL
2017-12-09 23:18 ` Ezequiel Garcia
2017-12-10 14:17 ` Miquel RAYNAL
2017-12-11 12:30 ` Ezequiel Garcia
2017-12-11 13:13 ` Miquel RAYNAL
2017-12-11 16:08 ` Ezequiel Garcia
2017-12-11 16:41 ` Miquel RAYNAL
[not found] ` <CAL92e2W7fLjVOWFgH2PpRLRP7Tf5L1vta0jduWm+bTVm647MNQ@mail.gmail.com>
2017-12-11 16:24 ` Ezequiel Garcia
2017-12-11 16:45 ` Boris Brezillon
2017-12-11 21:16 ` Boris Brezillon
2017-12-12 6:01 ` Greg Cook
2017-12-12 7:09 ` Ezequiel Garcia
2017-12-12 7:30 ` Greg Cook
2017-12-12 8:15 ` Boris Brezillon
2017-12-12 16:22 ` Ezequiel Garcia
2017-12-12 6:36 ` Sean Nyekjær
2017-12-12 6:50 ` Ezequiel Garcia
2017-12-12 7:17 ` Greg Cook
2017-12-09 23:04 ` Ezequiel Garcia
2017-12-09 23:22 ` Ezequiel Garcia
2017-12-09 23:24 ` Ezequiel Garcia
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