Re: [BUG] pxa3xx: wait time out when scanning for bb

From: Miquel RAYNAL <miquel.raynal@free-electrons.com>
To: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Cc: "Sean Nyekjær" <sean.nyekjaer@prevas.dk>,
	"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
	"Kasper Revsbech (KREV)" <krev@triax.com>,
	"Ezequiel Garcia" <ezequiel.garcia@free-electrons.com>
Subject: Re: [BUG] pxa3xx: wait time out when scanning for bb
Date: Sun, 10 Dec 2017 15:17:34 +0100	[thread overview]
Message-ID: <20171210151734.7e1aac59@xps13> (raw)
In-Reply-To: <CAAEAJfBGG9wMVGnwSBfgr+tpr_E_weVBqTc=EvDGU6JUQveFQg@mail.gmail.com>

Hi Ezequiel,

> >> [    2.296924] nand: device found, Manufacturer ID: 0x2c, Chip ID:
> >> 0xda [    2.303311] nand: Micron MT29F2G08ABAEAH4
> >> [    2.307334] nand: 256 MiB, SLC, erase size: 128 KiB, page size:
> >> 2048, OOB size: 64
> >> [    2.314939] pxa3xx-nand f10d0000.flash: ECC strength 16, ECC
> >> step size 2048  
> >
> > In theory, Marvell NAND flash controller does support 16-bit
> > strength per 512 bytes over 2048 bytes pages. However, this
> > controller driver (pxa3xx_nand) does not. See [1] for the supported
> > configurations. 
> 
> Why do you say the driver does not support it?

My reading of the trace was incomplete as it is mentioned that the
16-bit correction applies on 2kiB chunks (a full page) while I was
referring to 512 bytes chunks.

Protecting 2kiB pages with BCH algorithm may prevent the flip of up to
16 bits per page, which may also be seen as 4 bits per 512 bytes.
Asking for 16-bit strength for 512 bytes (configuration I was referring
to) is supported by the controller but simply not implemented.

However, below code setting up ecc->strength to 16 while ecc_stepsize is
512 is, IMHO, wrong.

> 
> It's automatically selecting this:
> 
>         /*
>          * Required ECC: 4-bit correction per 512 bytes
>          * Select: 16-bit correction per 2048 bytes
>          */
>         } else if (strength == 4 && ecc_stepsize == 512 && page_size
> == 2048) { info->ecc_bch = 1;
>                 info->chunk_size = 2048;
>                 info->spare_size = 32;
>                 info->ecc_size = 32;
>                 ecc->mode = NAND_ECC_HW;
>                 ecc->size = info->chunk_size;
>                 ecc->layout = &ecc_layout_2KB_bch4bit;
>                 ecc->strength = 16;
> 
> Otherwise, you would have seen the "ECC strength ... at page size ...
> is not supported"
> 
> > The ECC strength shown here is probably the best to use with this
> > type of NAND device but I suggest you try with 4b/512B by using
> > these two properties like in [2]:
> >
> >         nand-ecc-strength = <4>;
> >         nand-ecc-step-size = <512>;
> >
> >
> > Thanks,
> > Miquèl
> >
> > [1]
> > http://elixir.free-electrons.com/linux/v4.14/source/drivers/mtd/nand/pxa3xx_nand.c#L1575
> >
> > [2]
> > http://elixir.free-electrons.com/linux/v4.14/source/arch/arm/boot/dts/armada-385-db-ap.dts#L172
> >
> > ______________________________________________________
> > Linux MTD discussion mailing list
> > http://lists.infradead.org/mailman/listinfo/linux-mtd/  
> 
> 
> 

-- 
Miquel Raynal, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com