From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com ([134.134.136.24]) by bombadil.infradead.org with esmtps (Exim 4.89 #1 (Red Hat Linux)) id 1egTUk-0007TN-B8 for linux-mtd@lists.infradead.org; Tue, 30 Jan 2018 10:50:33 +0000 Date: Tue, 30 Jan 2018 12:50:13 +0200 From: Mika Westerberg To: linux-mtd@lists.infradead.org Cc: Cyrille Pitchen , Marek Vasut , David Woodhouse , Brian Norris , Boris Brezillon , Richard Weinberger , Anthony Wong , Bin Meng Subject: Re: [PATCH 1/3] spi-nor: intel-spi: Prefer WREN over other write enables Message-ID: <20180130105013.GH27654@lahna.fi.intel.com> References: <20180104090744.67654-1-mika.westerberg@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180104090744.67654-1-mika.westerberg@linux.intel.com> List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Thu, Jan 04, 2018 at 12:07:42PM +0300, Mika Westerberg wrote: > On many older systems using SW sequencer the PREOP_OPTYPE register > contains two preopcodes as following: > > PREOP_OPTYPE=0xf2785006 > > The last two bytes are the opcodes decoded to: > > 0x50 - Write enable for volatile status register > 0x06 - Write enable > > The former is used to modify volatile bits in the status register. For > non-volatile bits the latter is needed. Preopcodes are used in SW > sequencer to send one command "atomically" without anything else > interfering the transfer. The sequence that gets executed is: > > - Send preopcode (write enable) from PREOP_OPTYPE register > - Send the actual SPI command > - Poll busy bit in the status register (0x05, RDSR) > > Commit 8c473dd61bb5 ("spi-nor: intel-spi: Don't assume OPMENU0/1 to be > programmed by BIOS") enabled atomic sequence handling but because both > preopcodes are programmed, the following happens: > > if (preop >> 8) > val |= SSFSTS_CTL_SPOP; > > Since on these systems preop >> 8 == 0x50 we end up picking volatile > write enable instead. Because of this the actual write command is pretty > much NOP unless there is a WREN latched in the chip already. > > Fix this by preferring WREN over other write enable preopcodes. > > Fixes: 8c473dd61bb5 ("spi-nor: intel-spi: Don't assume OPMENU0/1 to be programmed by BIOS") > Signed-off-by: Mika Westerberg > Cc: stable@vger.kernel.org Hi, Any change getting these merged for v4.16?