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From: Boris Brezillon <boris.brezillon@bootlin.com>
To: Peter Rosin <peda@axentia.se>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Josh Wu <rainyfeeling@outlook.com>,
	Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>,
	linux-kernel@vger.kernel.org,
	Nicolas Ferre <nicolas.ferre@microchip.com>,
	Marek Vasut <marek.vasut@gmail.com>,
	linux-mtd@lists.infradead.org,
	Richard Weinberger <richard@nod.at>,
	Brian Norris <computersforpeace@gmail.com>,
	David Woodhouse <dwmw2@infradead.org>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma
Date: Mon, 2 Apr 2018 14:22:49 +0200	[thread overview]
Message-ID: <20180402142249.7e076a64@bbrezillon> (raw)
In-Reply-To: <b740406a-e91c-67ad-24a3-cbdbe259d00d@axentia.se>

On Thu, 29 Mar 2018 16:27:12 +0200
Peter Rosin <peda@axentia.se> wrote:

> On 2018-03-29 15:44, Boris Brezillon wrote:
> > On Thu, 29 Mar 2018 15:37:43 +0200
> > Peter Rosin <peda@axentia.se> wrote:
> >   
> >> On 2018-03-29 15:33, Boris Brezillon wrote:  
> >>> On Thu, 29 Mar 2018 15:10:54 +0200
> >>> Peter Rosin <peda@axentia.se> wrote:
> >>>     
> >>>> On a sama5d31 with a Full-HD dual LVDS panel (132MHz pixel clock) NAND
> >>>> flash accesses have a tendency to cause display disturbances. Add a
> >>>> module param to disable DMA from the NAND controller, since that fixes
> >>>> the display problem for me.
> >>>>
> >>>> Signed-off-by: Peter Rosin <peda@axentia.se>
> >>>> ---
> >>>>  drivers/mtd/nand/raw/atmel/nand-controller.c | 7 ++++++-
> >>>>  1 file changed, 6 insertions(+), 1 deletion(-)
> >>>>
> >>>> diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
> >>>> index b2f00b398490..2ff7a77c7b8e 100644
> >>>> --- a/drivers/mtd/nand/raw/atmel/nand-controller.c
> >>>> +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
> >>>> @@ -129,6 +129,11 @@
> >>>>  #define DEFAULT_TIMEOUT_MS			1000
> >>>>  #define MIN_DMA_LEN				128
> >>>>  
> >>>> +static bool atmel_nand_avoid_dma __read_mostly;
> >>>> +
> >>>> +MODULE_PARM_DESC(avoiddma, "Avoid using DMA");
> >>>> +module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400);    
> >>>
> >>> I'm not a big fan of those driver specific cmdline parameters. Can't we
> >>> instead give an higher priority to HLCDC master using the bus matrix?    
> >>
> >> I don't know if it will be enough, but we sure can try. However, I have
> >> no idea how to do that. I will happily test stuff though...  
> > 
> > There's no interface to configure that from Linux, but you can try to
> > tweak it with devmem and if that does the trick, maybe we can expose a
> > way to configure that from Linux. For more details, see the "Bus Matrix
> > (MATRIX)" section in Atmel datasheets.  
> 
> I don't seem to succeed in changing the registers I think I need to change.
> I can poke the "Write Protection Mode Register" by writing MAT0 and MAT1 to
> it.

You mean 0x4D415400, right? ("MAT0" != 0x4D415400).

> But when I try to write to "Priority Registers B For Slaves" it doesn't
> take, regardless of write protect mode.

Did you check MATRIX_WPSR after writing to MATRIX_PRXSY?

> 
> Can the relevant bits only be written when the HLCDC is inactive or
> something?

I don't know, but maybe Nicolas does.

-- 
Boris Brezillon, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

  parent reply	other threads:[~2018-04-02 12:22 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-29 13:10 [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma Peter Rosin
2018-03-29 13:33 ` Boris Brezillon
2018-03-29 13:37   ` Peter Rosin
2018-03-29 13:44     ` Boris Brezillon
2018-03-29 14:27       ` Peter Rosin
2018-03-30 21:43         ` Peter Rosin
2018-04-02 12:22         ` Boris Brezillon [this message]
2018-04-02 17:59           ` Peter Rosin
2018-04-02 19:28             ` Boris Brezillon
2018-04-02 20:20               ` Boris Brezillon
2018-04-02 20:32                 ` Boris Brezillon
2018-04-03  6:11                 ` Peter Rosin
2018-04-03  7:18                   ` Boris Brezillon
2018-04-11 14:44                     ` Peter Rosin
2018-04-11 14:59                       ` Boris Brezillon
2018-04-11 15:10                         ` Peter Rosin
2018-04-11 15:34                           ` Boris Brezillon
2018-04-11 15:34                       ` Nicolas Ferre
2018-04-12  7:18                         ` Peter Rosin
2018-05-22 18:03                         ` Peter Rosin
2018-05-23 10:42                           ` Boris Brezillon
2018-05-25 14:51                         ` Tudor Ambarus
2018-05-26 17:40                           ` Peter Rosin
2018-05-27  9:18                           ` Peter Rosin
2018-05-27 22:11                             ` Peter Rosin
2018-05-28 10:10                               ` Peter Rosin
2018-05-28 14:27                                 ` Boris Brezillon
2018-05-28 15:52                                   ` Peter Rosin
2018-05-28 16:09                                     ` Boris Brezillon
2018-05-28 16:09                                     ` Nicolas Ferre
2018-05-29  6:30                                 ` Eugen Hristev
2018-05-29  7:10                                   ` Peter Rosin
2018-05-29  7:25                                     ` Eugen Hristev
2018-05-29 14:49                                   ` Boris Brezillon
2018-05-29 15:01                                     ` Eugen Hristev
2018-05-29 15:15                                       ` Boris Brezillon
2018-05-29 15:21                                         ` Eugen Hristev
2018-05-29 15:46                                           ` Boris Brezillon
2018-05-29 17:57                                             ` Boris Brezillon
2018-05-29 21:37                                               ` Peter Rosin
2018-06-04 15:46                                 ` Tudor Ambarus
2018-06-04 16:03                                   ` Boris Brezillon
2018-04-03  6:51                 ` Peter Rosin
2018-04-03  7:15                   ` Boris Brezillon
2018-04-03  7:32                     ` Boris Brezillon
2018-04-03  8:14                     ` Peter Rosin
2018-04-03  8:30                       ` Boris Brezillon
2018-04-02 20:23               ` Peter Rosin
2018-04-02 20:35                 ` Boris Brezillon
2018-04-03  7:18                 ` Alexandre Belloni
2018-04-03  8:37                   ` Peter Rosin
2018-03-29 14:20 ` Nicolas Ferre
2018-03-29 14:23   ` Peter Rosin
2018-03-29 14:29   ` Boris Brezillon
2018-06-18  8:39 ` Boris Brezillon
2018-06-18 14:00   ` Miquel Raynal
2018-06-25 12:31   ` Miquel Raynal

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