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 for linux-mtd@lists.infradead.org; Thu, 06 Sep 2018 20:44:55 +0000
Date: Thu, 6 Sep 2018 22:44:22 +0200
From: Boris Brezillon <boris.brezillon@bootlin.com>
To: Marcel Ziswiler <marcel@ziswiler.com>
Cc: linux-mtd@lists.infradead.org, Marcel Ziswiler
 <marcel.ziswiler@toradex.com>, Miquel Raynal <miquel.raynal@bootlin.com>,
 linux-kernel@vger.kernel.org, Marek Vasut <marek.vasut@gmail.com>, Brian
 Norris <computersforpeace@gmail.com>, Richard Weinberger <richard@nod.at>,
 David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH 2/2] mtd: nand: esmt: retrieve ecc requirements from 5th
 id byte
Message-ID: <20180906224422.4be710c8@bbrezillon>
In-Reply-To: <20180906084922.14845-2-marcel@ziswiler.com>
References: <20180906084922.14845-1-marcel@ziswiler.com>
 <20180906084922.14845-2-marcel@ziswiler.com>
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On Thu,  6 Sep 2018 10:49:22 +0200
Marcel Ziswiler <marcel@ziswiler.com> wrote:

> From: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> This patch enables support to read the ECC level from the NAND flash
> using ESMT SLC NAND ID byte 5 information as documented e.g. in the
> following data sheet:
> 
> https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F59L1G81LA(2Y).pdf
> 
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> 
> ---
> 
>  drivers/mtd/nand/raw/nand_esmt.c | 46 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 drivers/mtd/nand/raw/nand_esmt.c
> 
> diff --git a/drivers/mtd/nand/raw/nand_esmt.c b/drivers/mtd/nand/raw/nand_esmt.c
> new file mode 100644
> index 000000000000..360d351ac043
> --- /dev/null
> +++ b/drivers/mtd/nand/raw/nand_esmt.c
> @@ -0,0 +1,46 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 Toradex AG
> + *
> + * Author: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> + */
> +
> +#include <linux/mtd/rawnand.h>
> +
> +static void esmt_nand_decode_id(struct nand_chip *chip)
> +{
> +	nand_decode_ext_id(chip);
> +
> +	/* Extract ECC requirements from 5th id byte. */
> +	if (chip->id.len >= 5 && nand_is_slc(chip)) {
> +		chip->ecc_step_ds = 512;
> +		switch (chip->id.data[4] & 0x3) {
> +		case 0x0:
> +			chip->ecc_strength_ds = 4;
> +			break;
> +		case 0x1:
> +			chip->ecc_strength_ds = 2;
> +			break;
> +		case 0x2:
> +			chip->ecc_strength_ds = 1;
> +			break;
> +		default:
> +			WARN(1, "Could not get ECC info");
> +			chip->ecc_step_ds = 0;
> +			break;
> +		}
> +	}
> +}
> +
> +static int esmt_nand_init(struct nand_chip *chip)
> +{
> +	if (nand_is_slc(chip))
> +		chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
> +
> +	return 0;
> +}
> +
> +const struct nand_manufacturer_ops esmt_nand_manuf_ops = {
> +	.detect = esmt_nand_decode_id,
> +	.init = esmt_nand_init,
> +};

Looks like you forgot to hook the new esmt_nand_manuf_ops to the ESMT
entry (in the nand_manufacturer table), so as is, the patch is not
exactly adding support for ECC req parsing ;-).