From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.bootlin.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g4Udf-0006Ya-C8 for linux-mtd@lists.infradead.org; Mon, 24 Sep 2018 17:27:16 +0000 Date: Mon, 24 Sep 2018 19:26:32 +0200 From: Boris Brezillon To: Christophe Kerello Cc: Miquel Raynal , , , , , , , , , , Subject: Re: [PATCH 2/3] mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver Message-ID: <20180924192632.1d5754da@bbrezillon> In-Reply-To: <6df8455e-2fb2-e65c-a492-fba42a9453f3@st.com> References: <1537199260-7280-1-git-send-email-christophe.kerello@st.com> <1537199260-7280-3-git-send-email-christophe.kerello@st.com> <20180922154819.015dcca7@xps13> <6df8455e-2fb2-e65c-a492-fba42a9453f3@st.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Mon, 24 Sep 2018 18:36:36 +0200 Christophe Kerello wrote: > >> +static int stm32_fmc2_resume(struct device *dev) > >> +{ > >> + struct stm32_fmc2 *fmc2 = dev_get_drvdata(dev); > >> + int i, ret; > >> + > >> + pinctrl_pm_select_default_state(dev); > >> + > >> + ret = clk_prepare_enable(fmc2->clk); > >> + if (ret) { > >> + dev_err(dev, "can not enable the clock\n"); > >> + return ret; > >> + } > >> + > >> + stm32_fmc2_init(fmc2); > >> + stm32_fmc2_timings_init(fmc2); > >> + stm32_fmc2_setup(fmc2); > >> + > >> + for (i = 0; i < fmc2->ncs; i++) > >> + nand_reset(&fmc2->chip, i); > > > > This means you have one different NAND chip wired on each CS. > > > > We could have two CS wired to the same NAND chip. Calling nand_reset > > twice would be harmless but a lost of time. Actually, you have to call nand_reset() for each CS, otherwise not all dies are reset.