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Date: Wed, 7 Nov 2018 13:26:45 +0100
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: Christophe Kerello <christophe.kerello@st.com>, <richard@nod.at>,
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Subject: Re: [PATCH v2 2/3] mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND
 flash controller driver
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Hi Christophe,

Boris Brezillon <boris.brezillon@bootlin.com> wrote on Wed, 7 Nov 2018
13:23:42 +0100:

> On Wed, 7 Nov 2018 12:08:58 +0100
> Christophe Kerello <christophe.kerello@st.com> wrote:
>=20
> > >> +
> > >> +write_8bit:
> > >> +	for (i =3D 0; i < len; i++)
> > >> +		writeb_relaxed(p[i], io_addr_w);   =20
> > >=20
> > > Is 8bit access really enforced by the byte accessor? In this case, how
> > > can you be sure 32-bit accesses are doing the right thing? Isn't there
> > > a bit somewhere in the config reg to configure the bus width?
> > >    =20
> >=20
> > I have checked the framework after Miqu=C3=A8l comment sent on v1 =3D> =
"If you=20
> > selected BOUNCE_BUFFER in the options, buf is supposedly
> > aligned, or am I missing something?".
> >=20
> > After checking the framework, my understanding was:
> >   - In case of 8-bit access is requested, the framework provides no=20
> > guarantee on buf. To avoid any issue, I write byte per byte.
> >   - In case of 8-bit access is not requested, it means that the=20
> > framework will try to write data in the page or in the oob. When writin=
g=20
> > to oob, chip->oob_poi will be used and this buffer is aligned. When=20
> > writing to the page, as the driver enables NAND_USE_BOUNCE_BUFFER=20
> > option, buf is guarantee aligned. =20
>=20
> It's probably what happens right now, but there's no guarantee that all
> non-8-bit accesses will be provided a 32-bit aligned buffer. The only
> guarantee we provide is on buffer passed to the
> chip->ecc.read/write_xxx() hooks, and ->exec_op() can be used outside
> of the "page access" path.
>=20
> >=20
> > But, I agree that it would be safe to reconfigure the bus width in 8-bi=
t=20
> > before writing byte per byte in case of a 16-bit NAND is used. =20
>=20
> Yes, and I also think you should not base your is-aligned check on the
> force_8bit value. Use IS_ALIGNED() instead.

Maybe the "configure the bus in 8/16-bit" blocks could deserve a
helper. There is probably other locations within this driver with the
same logic?


Thanks,
Miqu=C3=A8l