Re: [EXT] Re: [RESEND PATCH V2 2/2] mtd: core: NAND filling block

Boris Brezillon
2019-01-25T14:16:13Z

On Fri, 25 Jan 2019 13:31:17 +0000
"Bean Huo (beanhuo)" <beanhuo@micron.com> wrote:

> Hi, Boris
>
> >
> >On Mon, 21 Jan 2019 10:04:15 +0000
> >"Bean Huo (beanhuo)" <beanhuo@micron.com> wrote:
> >
> >> Hi, Boris
> >>
> >> >On Fri, 18 Jan 2019 22:12:04 +0000
> >> >"Bean Huo (beanhuo)" <beanhuo@micron.com> wrote:
> >> >
> >> >> + /* Corrupt page0 and page1, in order to simulate an
> >> >> + * uncompleted eraseing scenario. Just for case of
> >> >> + * power loss hits while below programming. in this
> >> >> + * way, the PEB will be re-erased again.
> >> >> + */
> >> >> + empty_page_mask |= 0x3;
> >> >> + memset(data_buf, 0xAA, mtd->writesize);
> >> >
> >> >Why do you use the 0xaa pattern BTW?
> >>
> >> Random pattern or any pattern is ok. Just to fill in page.
> >
> >Let's use 0x0 then. This way all cells are actually in a "programmed"
> >state.
> The proposed solution is effective in addressing the problem. A 00h pattern would also
> work but it would add unnecessary stress to the device, by programming more memory cells.

Then add a comment explaining that. Oh, BTW, you'll anyway wear the
block out pretty quickly since you're always programming the same cells
to 0, right?

>
> >BTW, I'd still be interested in knowing more about the root cause of this
> >issue. What causes this wrong "cell is erased" detection in your chips? I thought
> >the ERASE operation was an iterative process and cells were being tested after
> >each step to know whether they are erased or not in order to decide to do
> >another step or stop.
> >Am I wrong? What happens here to cause this erroneous detection?
>
> I cannot comment on the details of the detection procedure, which is proprietary algorithm.

Which is a shame, but enough on that, I'm pissed off by Micron's
behavior and you already know it.

> The patch ensures that the erase detection is accurate.

As said in the other mail, I hope you're right...