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From: Piotr Sroka <piotrs@cadence.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Arnd Bergmann <arnd@arndb.de>,
	Boris Brezillon <bbrezillon@kernel.org>,
	Marcel Ziswiler <marcel.ziswiler@toradex.com>,
	Richard Weinberger <richard@nod.at>,
	linux-kernel@vger.kernel.org, Stefan Agner <stefan@agner.ch>,
	Marek Vasut <marek.vasut@gmail.com>,
	Paul Burton <paul.burton@mips.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	linux-mtd@lists.infradead.org, Dmitry Osipenko <digetx@gmail.com>,
	Brian Norris <computersforpeace@gmail.com>,
	David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH v2 1/2] mtd: nand: Add Cadence NAND controller driver
Date: Mon, 1 Jul 2019 11:21:36 +0100	[thread overview]
Message-ID: <20190701102135.GA20033@global.cadence.com> (raw)
In-Reply-To: <20190701120454.6c8ac48e@xps13>

The 07/01/2019 12:04, Miquel Raynal wrote:
>EXTERNAL MAIL
>
>
>Hi Piotr,
>
>Piotr Sroka <piotrs@cadence.com> wrote on Mon, 1 Jul 2019 10:51:45
>+0100:
>
>
>[...]
>> >> >> >
>> >> >> >This driver is way too massive, I am pretty sure it can shrink a
>> >> >> >little bit more.
>> >> >> >[...]
>> >> >> >
>> >> >> I will try to make it shorer but it will be difucult to achive. It is because - there are a lot of calculation needed for PHY      - ECC are interleaved with data (like on marvell-nand or gpmi-nand).
>> >> >>    Therefore:    + RAW mode is complicated    + protecting BBM increases number of lines of source code
>> >> >> - need to support two DMA engines internal and external (slave) We will see on next patch version what is the result.      That page layout looks:
>> >> >
>> >> >Maybe you don't need to support both internal and external DMA?
>> >> >
>> >> >I am pretty sure there are rooms for size reduction.
>> >>
>> >> I describe how it works in general and maybe you help me chose better solution.
>> >>
>> >> HW controller can work in 3 modes. PIO - can work in master or slave DMA
>> >> CDMA - needs Master DMA for accessing command descriptors.
>> >> Generic mode - can use only Slave DMA.
>> >>
>> >> Generic mode is neccessery to implement functions other than page
>> >> program, page read, block erase. So it is essential. I cannot avoid
>> >> to use Slave DMA.
>> >
>> >This deserves a nice comment at the top.
>> Ok I will add the modes description to cover letter. >
>
>Not only to the cover letter: People read the code. Interested people
>might also read the commit log which is quite easy to find. The cover
>letter however will just disappear in the history of the Internet. I
>would rather prefer you explain how the IP works at the top of the
>driver.
So I will add the modes description to both cover letter and 
at the top of the driver. 
>
>
>Thanks,
>Miquèl

Thanks,
Piotr 

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  reply	other threads:[~2019-07-01 10:22 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-19 16:14 [PATCH v2 0/2] mtd: nand: Add Cadence NAND controller driver Piotr Sroka
2019-02-19 16:18 ` [PATCH v2 1/2] " Piotr Sroka
2019-03-05 18:09   ` Miquel Raynal
2019-03-21  9:33     ` Piotr Sroka
2019-05-12 12:24       ` Miquel Raynal
2019-06-06 15:19         ` Piotr Sroka
2019-06-27 16:15           ` Miquel Raynal
2019-07-01  9:51             ` Piotr Sroka
2019-07-01 10:04               ` Miquel Raynal
2019-07-01 10:21                 ` Piotr Sroka [this message]
2019-02-19 16:19 ` [PATCH v2 2/2] dt-bindings: " Piotr Sroka
2019-02-22 20:40   ` Rob Herring
2019-06-07 16:08     ` Piotr Sroka

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