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19 Apr 2020 15:28:15 -0700 Received: from andy by smile with local (Exim 4.93) (envelope-from ) id 1jQIQD-001v9r-Qw; Mon, 20 Apr 2020 01:28:17 +0300 Date: Mon, 20 Apr 2020 01:28:17 +0300 From: Andy Shevchenko To: "Ramuthevar, Vadivel MuruganX" Subject: Re: [PATCH v2 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Message-ID: <20200419222817.GK185537@smile.fi.intel.com> References: <20200417082147.43384-1-vadivel.muruganx.ramuthevar@linux.intel.com> <20200417082147.43384-3-vadivel.muruganx.ramuthevar@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200417082147.43384-3-vadivel.muruganx.ramuthevar@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200419_152821_101197_F0DFB7BC X-CRM114-Status: GOOD ( 15.12 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cheol.yong.kim@intel.com, devicetree@vger.kernel.org, qi-ming.wu@intel.com, anders.roxell@linaro.org, vigneshr@ti.com, arnd@arndb.de, hauke.mehrtens@intel.com, richard@nod.at, brendanhiggins@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-mips@vger.kernel.org, boris.brezillon@collabora.com, linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com, tglx@linutronix.de, masonccyang@mxic.com.tw, piotrs@cadence.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On Fri, Apr 17, 2020 at 04:21:47PM +0800, Ramuthevar,Vadivel MuruganX wrote: > From: Ramuthevar Vadivel Murugan > > This patch adds the new IP of Nand Flash Controller(NFC) support > on Intel's Lightning Mountain(LGM) SoC. > > DMA is used for burst data transfer operation, also DMA HW supports > aligned 32bit memory address and aligned data access by default. > DMA burst of 8 supported. Data register used to support the read/write > operation from/to device. > > NAND controller driver implements ->exec_op() to replace legacy hooks, > these specific call-back method to execute NAND operations. I guess untested version slipped into mailing list... See below why. ... > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include Do you need this? > +#include > +#include > +#include > +#include > +#include > +#include Basically, do you need all of them? And maybe keep them in order? ... > +static int lgm_dma_init(struct device *dev, struct lgm_nand_host *lgm_host) > +{ > + int ret; > + > + /* Prepare for TX DMA: */ > + lgm_host->dma_tx = dma_request_chan(dev, "tx"); > + if (IS_ERR(lgm_host->dma_tx)) { > + ret = PTR_ERR(lgm_host->dma_tx); > + dev_err(dev, "can't get the TX DMA channel, error %d!\n", ret); > + goto err; > + } > + > + /* Prepare for RX: */ > + lgm_host->dma_rx = dma_request_chan(dev, "rx"); > + if (IS_ERR(lgm_host->dma_rx)) { > + ret = PTR_ERR(lgm_host->dma_rx); > + dev_err(dev, "can't get the RX DMA channel, error %d\n", ret); I suspect this error path hasn't been tested. I don't see where tx channel freeing is happening. > + goto err; > + } > + > + return 0; > +err: > + return ret; Redundant label. > +} ... > + res = devm_platform_ioremap_resource_byname(pdev, lgm_host->cs_name); > + lgm_host->nandaddr_va = res; > + nandaddr_pa = res->start; > + if (IS_ERR(lgm_host->nandaddr_va)) > + return PTR_ERR(lgm_host->nandaddr_va); I'm wondering what is this. How is it even compile? -- With Best Regards, Andy Shevchenko ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/