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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jTK1P-0008Ht-UK; Tue, 28 Apr 2020 06:47:11 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jTK1N-0008HI-22 for linux-mtd@lists.infradead.org; Tue, 28 Apr 2020 06:47:10 +0000 Received: from localhost (unknown [IPv6:2a01:e0a:2c:6930:5cf4:84a1:2763:fe0d]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: bbrezillon) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 100B62A121D; Tue, 28 Apr 2020 07:47:07 +0100 (BST) Date: Tue, 28 Apr 2020 08:47:04 +0200 From: Boris Brezillon To: "Ramuthevar, Vadivel MuruganX" Subject: Re: [PATCH v3 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Message-ID: <20200428084704.5e04232a@collabora.com> In-Reply-To: <38334812-21b9-5b2c-db84-01c9eacc84d0@linux.intel.com> References: <20200423162113.38055-1-vadivel.muruganx.ramuthevar@linux.intel.com> <20200423162113.38055-3-vadivel.muruganx.ramuthevar@linux.intel.com> <20200424183612.4cfdbb6a@collabora.com> <20200427175127.0518c193@xps13> <20200428082759.25065146@collabora.com> <38334812-21b9-5b2c-db84-01c9eacc84d0@linux.intel.com> Organization: Collabora X-Mailer: Claws Mail 3.17.5 (GTK+ 2.24.32; x86_64-redhat-linux-gnu) MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200427_234709_226276_03D2767C X-CRM114-Status: GOOD ( 15.70 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cheol.yong.kim@intel.com, devicetree@vger.kernel.org, masonccyang@mxic.com.tw, vigneshr@ti.com, arnd@arndb.de, hauke.mehrtens@intel.com, richard@nod.at, brendanhiggins@google.com, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, robh+dt@kernel.org, linux-mtd@lists.infradead.org, Miquel Raynal , tglx@linutronix.de, qi-ming.wu@intel.com, andriy.shevchenko@intel.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On Tue, 28 Apr 2020 14:40:58 +0800 "Ramuthevar, Vadivel MuruganX" wrote: > Hi Boris, > > On 28/4/2020 2:27 pm, Boris Brezillon wrote: > > On Tue, 28 Apr 2020 14:17:30 +0800 > > "Ramuthevar, Vadivel MuruganX" > > wrote: > > > >> Hi Miquel, > >> > >> Thank you very much for the review comments and your time... > >> > >> On 27/4/2020 11:51 pm, Miquel Raynal wrote: > >>> Hi Ramuthevar, > >>> > >>>>> +static int ebu_nand_probe(struct platform_device *pdev) > >>>>> +{ > >>>>> + struct device *dev = &pdev->dev; > >>>>> + struct ebu_nand_controller *ebu_host; > >>>>> + struct nand_chip *nand; > >>>>> + phys_addr_t nandaddr_pa; > >>>>> + struct mtd_info *mtd; > >>>>> + struct resource *res; > >>>>> + int ret; > >>>>> + u32 cs; > >>>>> + > >>>>> + ebu_host = devm_kzalloc(dev, sizeof(*ebu_host), GFP_KERNEL); > >>>>> + if (!ebu_host) > >>>>> + return -ENOMEM; > >>>>> + > >>>>> + ebu_host->dev = dev; > >>>>> + nand_controller_init(&ebu_host->controller); > >>>>> + > >>>>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ebunand"); > >>>>> + ebu_host->ebu_addr = devm_ioremap_resource(&pdev->dev, res); > >>>>> + if (IS_ERR(ebu_host->ebu_addr)) > >>>>> + return PTR_ERR(ebu_host->ebu_addr); > >>>>> + > >>>>> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsnand"); > >>>>> + ebu_host->nand_addr = devm_ioremap_resource(&pdev->dev, res); > >>>>> + if (IS_ERR(ebu_host->nand_addr)) > >>>>> + return PTR_ERR(ebu_host->nand_addr); > >>>>> + > >>>>> + ret = device_property_read_u32(dev, "nand,cs", &cs); > >>>> > >>>> CS ids should be encoded in the reg property (see [1]). > >>> > >>> Is it your choice to only support a single CS or is it actually a > >>> controller limitation? > >> > >> Yes , its controller limitation to support only one CS > > > > I'm pretty sure that's not true, otherwise you wouldn't have to select > > the CS you want to use :P. > > At a time it supports only one chip select. Yes, like 99% of the NAND controllers, but that doesn't mean you can't support multi-CS chips. All you have to do is attach an array of ebu_nand_cs to your ebu_nand_chip (as done in the atmel driver I pointed to). nand_operation.cs tells you which CS (index in your ebu_nand_cs array) a specific operation is targeting, and you can pick the right MMIO range/reg value based on that. ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/