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13 May 2020 08:34:02 -0700 Received: from andy by smile with local (Exim 4.93) (envelope-from ) id 1jYtOX-006Rw5-7D; Wed, 13 May 2020 18:34:05 +0300 Date: Wed, 13 May 2020 18:34:05 +0300 From: Andy Shevchenko To: "Ramuthevar, Vadivel MuruganX" Subject: Re: [PATCH v6 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Message-ID: <20200513153405.GS185537@smile.fi.intel.com> References: <20200513104615.7905-1-vadivel.muruganx.ramuthevar@linux.intel.com> <20200513104615.7905-3-vadivel.muruganx.ramuthevar@linux.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200513104615.7905-3-vadivel.muruganx.ramuthevar@linux.intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200513_083407_228959_59BED58C X-CRM114-Status: GOOD ( 14.10 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cheol.yong.kim@intel.com, devicetree@vger.kernel.org, qi-ming.wu@intel.com, anders.roxell@linaro.org, vigneshr@ti.com, arnd@arndb.de, hauke.mehrtens@intel.com, richard@nod.at, brendanhiggins@google.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-mips@vger.kernel.org, boris.brezillon@collabora.com, linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com, tglx@linutronix.de, masonccyang@mxic.com.tw Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On Wed, May 13, 2020 at 06:46:15PM +0800, Ramuthevar,Vadivel MuruganX wrote: > From: Ramuthevar Vadivel Murugan > > This patch adds the new IP of Nand Flash Controller(NFC) support > on Intel's Lightning Mountain(LGM) SoC. > > DMA is used for burst data transfer operation, also DMA HW supports > aligned 32bit memory address and aligned data access by default. > DMA burst of 8 supported. Data register used to support the read/write > operation from/to device. > > NAND controller driver implements ->exec_op() to replace legacy hooks, > these specific call-back method to execute NAND operations. ... > +static int ebu_nand_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct ebu_nand_controller *ebu_host; > + struct nand_chip *nand; > + struct mtd_info *mtd; > + struct resource *res; > + char *resname; > + int ret, i; > + u32 reg; > + > + ebu_host = devm_kzalloc(dev, sizeof(*ebu_host), GFP_KERNEL); > + if (!ebu_host) > + return -ENOMEM; > + > + ebu_host->dev = dev; > + nand_controller_init(&ebu_host->controller); > + > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ebunand"); > + ebu_host->ebu = devm_ioremap_resource(&pdev->dev, res); devm_platform_ioremap_resource_byname > + if (IS_ERR(ebu_host->ebu)) > + return PTR_ERR(ebu_host->ebu); > + > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsnand"); > + ebu_host->hsnand = devm_ioremap_resource(&pdev->dev, res); devm_platform_ioremap_resource_byname > + if (IS_ERR(ebu_host->hsnand)) > + return PTR_ERR(ebu_host->hsnand); > + > + ret = device_property_read_u32(dev, "nand,cs", ®); > + if (ret) { > + dev_err(dev, "failed to get chip select: %d\n", ret); > + return ret; > + } > + ebu_host->cs_num = reg; > + > + for (i = 0; i < MAX_CS; i++) { > + resname = devm_kasprintf(dev, GFP_KERNEL, "nand_cs%d", i); > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, > + resname); if res is NULL? > + ebu_host->cs[i].chipaddr = devm_ioremap_resource(dev, res); > + ebu_host->cs[i].nand_pa = res->start; > + if (IS_ERR(ebu_host->cs[i].chipaddr)) > + return PTR_ERR(ebu_host->cs[i].chipaddr); Something happened with ordering / indentation along these lines... > + } > + > + for (i = 0; i < MAX_CS; i++) { > + resname = devm_kasprintf(dev, GFP_KERNEL, "addr_sel%d", i); > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, > + resname); if res is NULL? > + ebu_host->cs[i].addr_sel = res->start; > + writel(ebu_host->cs[i].addr_sel | EBU_ADDR_MASK(5) | > + EBU_ADDR_SEL_REGEN, ebu_host->ebu + EBU_ADDR_SEL(i)); > + } > + return ret; > +} ... > +static int ebu_nand_remove(struct platform_device *pdev) > +{ > + struct ebu_nand_controller *ebu_host = platform_get_drvdata(pdev); > + > + if (ebu_host) { How it can be NULL here? > + mtd_device_unregister(nand_to_mtd(&ebu_host->chip)); > + nand_cleanup(&ebu_host->chip); > + ebu_nand_disable(&ebu_host->chip); > + > + if (ebu_host->dma_rx || ebu_host->dma_tx) > + ebu_dma_cleanup(ebu_host); > + > + clk_disable_unprepare(ebu_host->clk); > + } > + > + return 0; > +} -- With Best Regards, Andy Shevchenko ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/