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Fri, 3 Jul 2020 06:19:26 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 3 Jul 2020 06:19:26 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 3 Jul 2020 06:19:26 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 063BJPDQ090174; Fri, 3 Jul 2020 06:19:25 -0500 Date: Fri, 3 Jul 2020 16:49:24 +0530 From: Pratyush Yadav To: Subject: Re: [PATCH 2/2] mtd: spi-nor: Disable the flash quad mode in spi_nor_restore() Message-ID: <20200703111924.tyrvzbbgd7ak53qf@ti.com> References: <1592312547-19239-1-git-send-email-yangyicong@hisilicon.com> <1592312547-19239-3-git-send-email-yangyicong@hisilicon.com> <193b32f7-f56d-4f78-5353-b5d47cbf71d6@microchip.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <193b32f7-f56d-4f78-5353-b5d47cbf71d6@microchip.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200703_071941_535647_2F674152 X-CRM114-Status: GOOD ( 15.66 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: vigneshr@ti.com, sergei.shtylyov@cogentembedded.com, richard@nod.at, me@yadavpratyush.com, john.garry@huawei.com, linuxarm@huawei.com, yangyicong@hisilicon.com, alexander.sverdlin@nokia.com, miquel.raynal@bootlin.com, linux-mtd@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On 02/07/20 11:02AM, Tudor.Ambarus@microchip.com wrote: > On 6/16/20 4:02 PM, Yicong Yang wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > If the flash's quad mode is enabled, it'll remain in the quad mode when > > it's removed. If we drive the flash next time in SPI/Dual mode, then > > problem occurs as the flash's quad enable bit is not cleared. > > Please describe the problems that occur. When QE bit is one the flash > operates in Standard/Dual/Quad SPI modes. WP# and RESET#/HOLD# are > affected as they change their functionality to IO2 and IO3 when QE > is 1. Is there anything else? IIUC if we do anything that introduces a state on the flash, we want to clear that state up on restore. That's what we (will) do for 8D mode and for 4-byte addressing mode. Does that not apply here? > While I find the intention good, there might be some problems here: > 1/ w25q jvm variants come with QE "fixed" to 1. This probably means > that QE is not writable, and a writing of QE to zero will be ignored, > but we have to check. In that case they shouldn't have a quad_enable() hook, no? > 2/S25FS128S: CR1NV[1] can set the default power-on state for the > CR1V[1] to 1, i.e. QE to be set to 1 at power-on by default. The > logic here complicates a bit, and maybe we'll have to amend the > patch. > > > > > Disable the quad mode in spi_nor_restore(), the flash will leave > > quad mode when remove. This will make sure the flash always enter the > > correct mode when loaded. > s/correct/ Standard/Dual SPI > > Cheers, > ta -- Regards, Pratyush Yadav Texas Instruments India ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/