Re: [PATCH 1/3] mtd: spi-nor: macronix: add support for Macronix octaflash

[Miquel Raynal <miquel.raynal@bootlin.com>]

> > +			SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_CR2, 1),
> > +				   SPI_MEM_OP_ADDR(4, SPINOR_REG_MXIC_CR2_DC, 1),
> > +				   SPI_MEM_OP_NO_DUMMY,
> > +				   SPI_MEM_OP_DATA_OUT(1, buf, 1));
> > +
> > +		ret = spi_mem_exec_op(nor->spimem, &op);
> > +		if (ret)
> > +			return ret;
> > +
> > +		ret = spi_nor_wait_till_ready(nor);
> > +		if (ret)
> > +			return ret;
> > +
> > +		nor->read_dummy = 20;  
> 
> I am not entirely convinced by this value, yet.
> 
> If I understand correctly your issue, the flash needs some extra time
> before receiving/sending data. You estimate it to be around 800ns
> (20 bytes @ 20MHz), so would it be possible to derive the minimum
> number of dummy cycles needed for the flash and use a dynamic value?
> Otherwise if the controller is not running at the maximum frequency
> you'll end up waiting a lot more than expected.

Just to clarify, I meant 20 bytes @ 200Mhz, not 20MHz, and I got
possibly fooled by the fact that we are talking about DDR mode, so
400ns is probably more accurate than 800. But no matter the actual
numbers, let's discuss the logic more than the values. 

Thanks,
Miquèl

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