Re: [PATCH 4/6] spi: spi-mem: reject partial cycle transfers in 8D-8D-8D mode

Mark Brown
2021-05-07T15:32:56Z

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On Fri, May 07, 2021 at 07:26:33PM +0530, Pratyush Yadav wrote:

> Patches 2 and 3 are a slightly different matter. They add an extra
> register write. But most controllers I've come across don't support
> 1-byte writes in 8D mode. It is likely that they are sending
> bogus/undefined values in the second byte and deasserting CS only after
> the cycle is done. So they should _in theory_ change undefined behaviour
> to defined behaviour.

> Still, they introduce an extra register write. I'm not sure how
> risk-tolerant you want to be for stable backports. I will leave the
> judgement to you or Tudor or Vignesh.

Ah, given that if nobody's seeing any issues I'd probably just hold off
there TBH.

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