From: Chris Morgan <macroalpha82@gmail.com>
To: linux-mtd@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org, andy.yan@rock-chips.com,
yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com,
tudor.ambarus@microchip.com, michael@walle.cc, p.yadav@ti.com,
heiko@sntech.de, robh+dt@kernel.org, vigneshr@ti.com,
richard@nod.at, miquel.raynal@bootlin.com,
Chris Morgan <macromorgan@hotmail.com>
Subject: [PATCH 3/3] arm64: dts: rockchip: Add SFC to PX30
Date: Wed, 26 May 2021 13:16:36 -0500 [thread overview]
Message-ID: <20210526181636.1130-4-macroalpha82@gmail.com> (raw)
In-Reply-To: <20210526181636.1130-1-macroalpha82@gmail.com>
From: Chris Morgan <macromorgan@hotmail.com>
Add a devicetree entry for the Rockchip SFC for the PX30 SOC.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
arch/arm64/boot/dts/rockchip/px30.dtsi | 38 ++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 09baa8a167ce..c0a551c9c043 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -966,6 +966,18 @@ emmc: mmc@ff390000 {
status = "disabled";
};
+ sfc: spi@ff3a0000 {
+ compatible = "rockchip,px30-sfc","rockchip,sfc";
+ reg = <0x0 0xff3a0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "sfc", "hsfc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>;
+ power-domains = <&power PX30_PD_MMC_NAND>;
+ status = "disabled";
+ };
+
nfc: nand-controller@ff3b0000 {
compatible = "rockchip,px30-nfc";
reg = <0x0 0xff3b0000 0x0 0x4000>;
@@ -1967,6 +1979,32 @@ flash_bus8: flash-bus8 {
};
};
+ serial_flash {
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins =
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ <1 RK_PA1 3 &pcfg_pull_none>,
+ <1 RK_PA2 3 &pcfg_pull_none>,
+ <1 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins =
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ <1 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs: sfc-cs {
+ rockchip,pins =
+ <1 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins =
+ <1 RK_PB1 3 &pcfg_pull_none>;
+ };
+ };
+
lcdc {
lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
rockchip,pins =
--
2.25.1
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prev parent reply other threads:[~2021-05-26 19:22 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-26 18:16 [PATCH 0/3] Add Rockchip SFC(serial flash controller) support Chris Morgan
2021-05-26 18:16 ` [PATCH 1/3] mtd: spi-nor: add rockchip serial flash controller driver Chris Morgan
2021-05-27 10:16 ` Pratyush Yadav
2021-05-26 18:16 ` [PATCH 2/3] mtd: spi-nor: Bindings for Rockchip serial flash controller Chris Morgan
2021-05-26 18:16 ` Chris Morgan [this message]
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