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From: Mark Brown <broonie@kernel.org>
To: Jon Lin <jon.lin@rock-chips.com>
Cc: linux-spi@vger.kernel.org, robh+dt@kernel.org, heiko@sntech.de,
	jbx6244@gmail.com, hjc@rock-chips.com,
	yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com,
	linux-rockchip@lists.infradead.org,
	linux-mtd@lists.infradead.org, p.yadav@ti.com,
	macroalpha82@gmail.com, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, mturquette@baylibre.com,
	sboyd@kernel.org, linux-clk@vger.kernel.org,
	Chris Morgan <macromorgan@hotmail.com>
Subject: Re: [RFC PATCH v11 02/10] spi: rockchip-sfc: add rockchip serial flash controller
Date: Wed, 7 Jul 2021 18:47:35 +0100	[thread overview]
Message-ID: <20210707174735.GL4394@sirena.org.uk> (raw)
In-Reply-To: <20210707090810.5717-3-jon.lin@rock-chips.com>


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On Wed, Jul 07, 2021 at 05:08:02PM +0800, Jon Lin wrote:

This looks pretty nice, a few small issues below but nothing major:

> +/* Maximum clock values from datasheet suggest keeping clock value under
> + * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver
> + * has a minimum of 10MHz and a default of 80MHz which seems reasonable.
> + */

It's OK to just not specify a minimum if the hardware doesn't have one,
and AFAICT the driver doesn't actually use the default speed (the SPI
stack will generally try to go as fast as possible by default, the board
can configure the maximum speed and should be doing that if there's
issues).

> +static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id)
> +{
> +	struct rockchip_sfc *sfc = dev_id;
> +	u32 reg;
> +
> +	reg = readl(sfc->regbase + SFC_RISR);
> +
> +	/* Clear interrupt */
> +	writel_relaxed(reg, sfc->regbase + SFC_ICLR);
> +
> +	if (reg & SFC_RISR_DMA)
> +		complete(&sfc->cp);
> +
> +	return IRQ_HANDLED;
> +}

This will unconditionally ack any interrupt that is flagged, and doesn't
verify that there were any at all.  This won't work if the interrupt
ever gets shared and will mean that if something goes wrong and an
unexpected interrupt happens we'll at best just ignore it, at worst
we'll end up with a screaming interrupt constantly firing.  It'd be
better to at least return IRQ_NONE if we got anything unexpected (I
guess just if SFC_RISR_DMA isn't set, assuming there's nothing else
we're intentionally ignoring).

> +	master->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | SPI_RX_DUAL;

Should it also do SPI_HALF_DUPLEX?

> +	ret = devm_request_irq(dev, ret, rockchip_sfc_irq_handler,
> +			       0, pdev->name, sfc);
> +	if (ret) {
> +		dev_err(dev, "Failed to request irq\n");
> +
> +		return ret;
> +	}

Should we have a call to _irq_mask() before this to make sure that the
mask is set up correctly in the hardware, just in case?

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  reply	other threads:[~2021-07-07 17:49 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-07  9:08 [RFC PATCH v11 00/10] Add Rockchip SFC(serial flash controller) support Jon Lin
2021-07-07  9:08 ` [RFC PATCH v11 01/10] dt-bindings: rockchip-sfc: Bindings for Rockchip serial flash controller Jon Lin
2021-07-12 16:19   ` Rob Herring
2021-07-07  9:08 ` [RFC PATCH v11 02/10] spi: rockchip-sfc: add rockchip " Jon Lin
2021-07-07 17:47   ` Mark Brown [this message]
2021-07-07  9:08 ` [RFC PATCH v11 03/10] arm64: dts: rockchip: Add SFC to PX30 Jon Lin
2021-07-07  9:08 ` [RFC PATCH v11 04/10] clk: rockchip: rk3036: fix up the sclk_sfc parent error Jon Lin
2021-07-07  9:08 ` [RFC PATCH v11 05/10] clk: rockchip: add dt-binding for hclk_sfc on rk3036 Jon Lin
2021-07-07  9:08   ` [RFC PATCH v11 06/10] clk: rockchip: Add support " Jon Lin
2021-07-07  9:08   ` [RFC PATCH v11 07/10] arm: dts: rockchip: Add SFC to RK3036 Jon Lin
2021-07-07  9:08   ` [RFC PATCH v11 08/10] arm: dts: rockchip: Add SFC to RV1108 Jon Lin
2021-07-07  9:08   ` [RFC PATCH v11 09/10] arm64: dts: rockchip: Add SFC to RK3308 Jon Lin
2021-07-07  9:09   ` [RFC PATCH v11 10/10] arm64: dts: rockchip: Enable SFC for Odroid Go Advance Jon Lin
2021-07-07 17:04     ` Chris Morgan

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