From: Tudor Ambarus <tudor.ambarus@microchip.com>
To: <michael@walle.cc>, <vigneshr@ti.com>, <p.yadav@ti.com>
Cc: <figgyc@figgyc.uk>, <mail@david-bauer.net>,
<linux@rasmusvillemoes.dk>, <esben@geanix.com>,
<knaerzche@gmail.com>, <code@reto-schneider.ch>,
<zhengxunli@mxic.com.tw>, <jaimeliao@mxic.com.tw>,
<heiko.thiery@gmail.com>, <macromorgan@hotmail.com>, <sr@denx.de>,
<miquel.raynal@bootlin.com>, <richard@nod.at>,
<linux-mtd@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<nicolas.ferre@microchip.com>,
"Tudor Ambarus" <tudor.ambarus@microchip.com>
Subject: [PATCH v2 18/35] mtd: spi-nor: Get rid of SPI_NOR_4B_OPCODES flag
Date: Tue, 27 Jul 2021 07:52:05 +0300 [thread overview]
Message-ID: <20210727045222.905056-19-tudor.ambarus@microchip.com> (raw)
In-Reply-To: <20210727045222.905056-1-tudor.ambarus@microchip.com>
Get rid of flash_info flags that indicate settings which can be
discovered when parsing SFDP. It will be clearer who sets what,
and we'll restrict the flash settings that a developer can choose to
only settings that are not SFDP discoverable.
Whether a flash supports 4byte opcodes or not, is discoverable when
parsing the optional 4-byte address instruction table. Flashes that
do not support the 4bait SFDP table should set the SNOR_F_4B_OPCODES
flag in the late_init() call. Flashes that define the 4bait SFDP table
but gets it wrong, should set the flag in a post_sfdp fixup hook.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
drivers/mtd/spi-nor/core.c | 3 ---
drivers/mtd/spi-nor/core.h | 32 ++++++++++++++++----------------
drivers/mtd/spi-nor/gigadevice.c | 7 ++++---
drivers/mtd/spi-nor/issi.c | 12 ++++++------
drivers/mtd/spi-nor/macronix.c | 18 ++++++++++--------
drivers/mtd/spi-nor/micron-st.c | 22 +++++++++++++---------
drivers/mtd/spi-nor/spansion.c | 12 ++++++------
7 files changed, 55 insertions(+), 51 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 6a8617346764..240d5c31af88 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -3204,9 +3204,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
if (ret)
return ret;
- if (info->flags & SPI_NOR_4B_OPCODES)
- nor->flags |= SNOR_F_4B_OPCODES;
-
if (info->flags & SPI_NOR_IO_MODE_EN_VOLATILE)
nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE;
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 625f4eed75f1..dfdc51a26cad 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -348,40 +348,36 @@ struct flash_info {
* S3AN flashes have specific opcode to
* read the status register.
*/
-#define SPI_NOR_4B_OPCODES BIT(11) /*
- * Use dedicated 4byte address op codes
- * to support memory size above 128Mib.
- */
-#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
-#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
-#define USE_CLSR BIT(14) /* use CLSR command */
-#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
-#define SPI_NOR_TB_SR_BIT6 BIT(16) /*
+#define NO_CHIP_ERASE BIT(11) /* Chip does not support chip erase */
+#define SPI_NOR_SKIP_SFDP BIT(12) /* Skip parsing of SFDP tables */
+#define USE_CLSR BIT(13) /* use CLSR command */
+#define SPI_NOR_OCTAL_READ BIT(14) /* Flash supports Octal Read */
+#define SPI_NOR_TB_SR_BIT6 BIT(15) /*
* Top/Bottom (TB) is bit 6 of
* status register. Must be used with
* SPI_NOR_HAS_TB.
*/
-#define SPI_NOR_4BIT_BP BIT(17) /*
+#define SPI_NOR_4BIT_BP BIT(16) /*
* Flash SR has 4 bit fields (BP0-3)
* for block protection.
*/
-#define SPI_NOR_BP3_SR_BIT6 BIT(18) /*
+#define SPI_NOR_BP3_SR_BIT6 BIT(17) /*
* BP3 is bit 6 of status register.
* Must be used with SPI_NOR_4BIT_BP.
*/
-#define SPI_NOR_OCTAL_DTR_READ BIT(19) /* Flash supports octal DTR Read. */
-#define SPI_NOR_OCTAL_DTR_PP BIT(20) /* Flash supports Octal DTR Page Program */
-#define SPI_NOR_IO_MODE_EN_VOLATILE BIT(21) /*
+#define SPI_NOR_OCTAL_DTR_READ BIT(18) /* Flash supports octal DTR Read. */
+#define SPI_NOR_OCTAL_DTR_PP BIT(19) /* Flash supports Octal DTR Page Program */
+#define SPI_NOR_IO_MODE_EN_VOLATILE BIT(20) /*
* Flash enables the best
* available I/O mode via a
* volatile bit.
*/
-#define SPI_NOR_SWP_IS_VOLATILE BIT(22) /*
+#define SPI_NOR_SWP_IS_VOLATILE BIT(21) /*
* Flash has volatile software write
* protection bits. Usually these will
* power-up in a write-protected state.
*/
-#define SPI_NOR_PARSE_SFDP BIT(23) /*
+#define SPI_NOR_PARSE_SFDP BIT(22) /*
* Flash initialized based on the SFDP
* tables.
*/
@@ -569,4 +565,8 @@ static struct spi_nor __maybe_unused *mtd_to_spi_nor(struct mtd_info *mtd)
return mtd->priv;
}
+static inline void snor_f_4b_opcodes(struct spi_nor *nor)
+{
+ nor->flags |= SNOR_F_4B_OPCODES;
+}
#endif /* __LINUX_MTD_SPI_NOR_INTERNAL_H */
diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
index 447d84bb2128..ff523fe734ef 100644
--- a/drivers/mtd/spi-nor/gigadevice.c
+++ b/drivers/mtd/spi-nor/gigadevice.c
@@ -47,9 +47,10 @@ static const struct flash_info gigadevice_parts[] = {
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
{ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
- SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
- .fixups = &gd25q256_fixups },
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+ SPI_NOR_TB_SR_BIT6)
+ .fixups = &gd25q256_fixups,
+ .late_init = snor_f_4b_opcodes, },
};
const struct spi_nor_manufacturer spi_nor_gigadevice = {
diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
index 1e5bb5408b68..aeff8f60cbae 100644
--- a/drivers/mtd/spi-nor/issi.c
+++ b/drivers/mtd/spi-nor/issi.c
@@ -45,9 +45,9 @@ static const struct flash_info issi_parts[] = {
{ "is25lp128", INFO(0x9d6018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ) },
{ "is25lp256", INFO(0x9d6019, 0, 64 * 1024, 512,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_4B_OPCODES)
- .fixups = &is25lp256_fixups },
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ .fixups = &is25lp256_fixups,
+ .late_init = snor_f_4b_opcodes, },
{ "is25wp032", INFO(0x9d7016, 0, 64 * 1024, 64,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "is25wp064", INFO(0x9d7017, 0, 64 * 1024, 128,
@@ -55,9 +55,9 @@ static const struct flash_info issi_parts[] = {
{ "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_4B_OPCODES)
- .fixups = &is25lp256_fixups },
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ .fixups = &is25lp256_fixups,
+ .late_init = snor_f_4b_opcodes, },
/* PMC */
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index fba85efafb47..9709eb68b613 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -105,29 +105,31 @@ static const struct flash_info macronix_parts[] = {
{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
.fixups = &mx25l25635_fixups },
- { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512,
- SECT_4K | SPI_NOR_4B_OPCODES) },
+ { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K)
+ .late_init = snor_f_4b_opcodes, },
{ "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SPI_NOR_QUAD_READ)
+ .late_init = snor_f_4b_opcodes, },
{ "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16,
SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
{ "mx66l51235f", INFO(0xc2201a, 0, 64 * 1024, 1024,
- SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_4B_OPCODES) },
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ .late_init = snor_f_4b_opcodes, },
{ "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SPI_NOR_QUAD_READ)
+ .late_init = snor_f_4b_opcodes, },
{ "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048,
SPI_NOR_QUAD_READ) },
{ "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096,
- SECT_4K | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ .late_init = snor_f_4b_opcodes, },
};
static void macronix_default_init(struct spi_nor *nor)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index c224e59820a1..72cc4673bf88 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -121,13 +121,13 @@ static struct spi_nor_fixups mt35xu512aba_fixups = {
static const struct flash_info micron_parts[] = {
{ "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
- SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ |
- SPI_NOR_OCTAL_DTR_PP |
+ SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP |
SPI_NOR_IO_MODE_EN_VOLATILE)
- .fixups = &mt35xu512aba_fixups},
+ .fixups = &mt35xu512aba_fixups,
+ .late_init = snor_f_4b_opcodes, },
{ "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048,
- SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
- SPI_NOR_4B_OPCODES) },
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ)
+ .late_init = snor_f_4b_opcodes, },
};
static const struct flash_info st_parts[] = {
@@ -149,25 +149,29 @@ static const struct flash_info st_parts[] = {
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SPI_NOR_QUAD_READ)
+ .late_init = snor_f_4b_opcodes, },
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
USE_FSR | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ) },
{ "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512,
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SPI_NOR_QUAD_READ)
+ .late_init = snor_f_4b_opcodes, },
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512,
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SPI_NOR_QUAD_READ)
+ .late_init = snor_f_4b_opcodes, },
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024,
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) },
{ "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SPI_NOR_QUAD_READ)
+ .late_init = snor_f_4b_opcodes, },
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024,
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index aad7170768b4..af10833f56d8 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -259,14 +259,14 @@ static const struct flash_info spansion_parts[] = {
{ "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16,
SECT_4K | SPI_NOR_DUAL_READ) },
{ "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_4B_OPCODES) },
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ .late_init = snor_f_4b_opcodes, },
{ "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_4B_OPCODES) },
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ .late_init = snor_f_4b_opcodes, },
{ "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_4B_OPCODES) },
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ .late_init = snor_f_4b_opcodes, },
{ "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1,
SPI_NOR_NO_ERASE) },
{ "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256,
--
2.25.1
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next prev parent reply other threads:[~2021-07-27 5:51 UTC|newest]
Thread overview: 133+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-27 4:51 [PATCH v2 00/35] mtd: spi-nor: Handle ID collisions and clean params init Tudor Ambarus
2021-07-27 4:51 ` [PATCH v2 01/35] mtd: spi-nor: core: Introduce SPI_NOR_PARSE_SFDP Tudor Ambarus
2021-08-04 8:09 ` Pratyush Yadav
2021-08-23 22:17 ` Michael Walle
2021-07-27 4:51 ` [PATCH v2 02/35] mtd: spi-nor: core: Report correct name in case of ID collisions Tudor Ambarus
2021-08-04 8:23 ` Pratyush Yadav
2021-08-23 22:32 ` Michael Walle
2021-07-27 4:51 ` [PATCH v2 03/35] mtd: spi-nor: macronix: Handle ID collision b/w MX25L3233F and MX25L3205D Tudor Ambarus
2021-08-23 22:42 ` Michael Walle
2021-10-01 8:41 ` Tudor.Ambarus
2021-07-27 4:51 ` [PATCH v2 04/35] mtd: spi-nor: macronix: Handle ID collision b/w MX25L12805D and MX25L12835F Tudor Ambarus
2021-08-23 22:44 ` Michael Walle
2021-07-27 4:51 ` [PATCH v2 05/35] mtd: spi-nor: Introduce Manufacturer ID collisions driver Tudor Ambarus
2021-08-16 18:28 ` Pratyush Yadav
2021-08-23 22:47 ` Michael Walle
2021-10-01 9:16 ` Tudor.Ambarus
2021-10-24 17:44 ` Michael Walle
2021-11-06 9:58 ` Tudor.Ambarus
2021-07-27 4:51 ` [PATCH v2 06/35] mtd: spi-nor: manuf-id-collisions: Add support for xt25f128b Tudor Ambarus
2021-07-27 15:52 ` Chris Morgan
2021-07-28 4:10 ` Tudor.Ambarus
2021-08-16 18:43 ` Pratyush Yadav
2021-10-01 9:26 ` Tudor.Ambarus
2021-07-27 4:51 ` [PATCH v2 07/35] mtd: spi-nor: manuf-id-collisions: Add support for xm25qh64c Tudor Ambarus
2021-08-16 18:45 ` Pratyush Yadav
2021-07-27 4:51 ` [PATCH v2 08/35] mtd: spi-nor: core: Introduce the ate_init() hook Tudor Ambarus
2021-08-16 18:54 ` Pratyush Yadav
2021-09-09 21:40 ` Michael Walle
2021-10-01 9:44 ` Tudor.Ambarus
2021-10-01 9:38 ` Tudor.Ambarus
2021-07-27 4:51 ` [PATCH v2 09/35] mtd: spi-nor: atmel: Use flash late_init() for locking Tudor Ambarus
2021-08-16 19:06 ` Pratyush Yadav
2021-09-09 21:44 ` Michael Walle
2021-10-01 11:40 ` Tudor.Ambarus
2021-10-02 12:58 ` Michael Walle
2021-10-11 6:27 ` Pratyush Yadav
2021-07-27 4:51 ` [PATCH v2 10/35] mtd: spi-nor: sst: " Tudor Ambarus
2021-08-16 19:09 ` Pratyush Yadav
2021-10-01 11:43 ` Tudor.Ambarus
2021-10-01 12:19 ` Pratyush Yadav
2021-09-09 21:52 ` Michael Walle
2021-07-27 4:51 ` [PATCH v2 11/35] mtd: spi-nor: winbond: Use manufacturer late_init() for OTP ops Tudor Ambarus
2021-08-16 19:17 ` Pratyush Yadav
2021-09-09 21:50 ` Michael Walle
2021-10-01 11:58 ` Tudor.Ambarus
2021-10-01 11:54 ` Tudor.Ambarus
2021-10-11 6:54 ` Pratyush Yadav
2021-07-27 4:51 ` [PATCH v2 12/35] mtd: spi-nor: xilinx: Use manufacturer late_init() to set setup method Tudor Ambarus
2021-08-16 19:19 ` Pratyush Yadav
2021-09-09 21:53 ` Michael Walle
2021-07-27 4:52 ` [PATCH v2 13/35] mtd: spi-nor: sst: Use manufacturer late_init() to set _write() Tudor Ambarus
2021-08-16 19:20 ` Pratyush Yadav
2021-09-09 21:54 ` Michael Walle
2021-07-27 4:52 ` [PATCH v2 14/35] mtd: spi-nor: spansion: Use manufacturer late_init() Tudor Ambarus
2021-08-16 19:22 ` Pratyush Yadav
2021-09-09 22:02 ` Michael Walle
2021-10-01 12:14 ` Tudor.Ambarus
2021-10-02 13:14 ` Michael Walle
2021-07-27 4:52 ` [PATCH v2 15/35] mtd: spi-nor: core: Call spi_nor_post_sfdp_fixups() only when SFDP is defined Tudor Ambarus
2021-08-16 19:31 ` Pratyush Yadav
2021-10-01 12:31 ` Tudor.Ambarus
2021-07-27 4:52 ` [PATCH v2 16/35] mtd: spi-nor: core: Mark default_init() as deprecated Tudor Ambarus
2021-08-16 19:36 ` Pratyush Yadav
2021-10-01 14:18 ` Tudor.Ambarus
2021-10-01 17:06 ` Pratyush Yadav
2021-07-27 4:52 ` [PATCH v2 17/35] mtd: spi-nor: Introduce spi_nor_nonsfdp_flags_init() Tudor Ambarus
2021-08-17 10:24 ` Pratyush Yadav
2021-08-17 12:15 ` Tudor.Ambarus
2021-10-22 11:21 ` Michael Walle
2021-10-22 12:10 ` Pratyush Yadav
2021-10-22 12:42 ` Tudor.Ambarus
2021-10-22 12:59 ` Michael Walle
2021-10-22 13:25 ` Tudor.Ambarus
2021-10-24 17:05 ` Michael Walle
2021-10-25 12:18 ` Tudor.Ambarus
2021-07-27 4:52 ` Tudor Ambarus [this message]
2021-08-17 12:16 ` [PATCH v2 18/35] mtd: spi-nor: Get rid of SPI_NOR_4B_OPCODES flag Pratyush Yadav
2021-10-04 3:18 ` Tudor.Ambarus
2021-10-19 17:26 ` Pratyush Yadav
2021-10-20 9:55 ` Tudor.Ambarus
2021-10-21 8:44 ` Tudor.Ambarus
2021-10-21 9:30 ` Pratyush Yadav
2021-10-22 11:37 ` Michael Walle
2021-10-22 12:43 ` Tudor.Ambarus
2021-07-27 4:52 ` [PATCH v2 19/35] mtd: spi-nor: Get rid of SPI_NOR_IO_MODE_EN_VOLATILE flag Tudor Ambarus
2021-08-17 12:21 ` Pratyush Yadav
2021-10-04 3:52 ` Tudor.Ambarus
2021-10-11 6:15 ` Pratyush Yadav
2021-07-27 4:52 ` [PATCH v2 20/35] mtd: spi-nor: core: Use container_of to get the pointer to struct spi_nor Tudor Ambarus
2021-07-27 7:08 ` Rasmus Villemoes
2021-10-22 8:00 ` Tudor.Ambarus
2021-08-17 12:23 ` Pratyush Yadav
2021-07-27 4:52 ` [PATCH v2 21/35] mtd: spi-nor: Introduce spi_nor_set_mtd_info() Tudor Ambarus
2021-08-16 7:25 ` Tudor.Ambarus
2021-08-17 16:23 ` Pratyush Yadav
2021-10-22 11:53 ` Michael Walle
2021-07-27 4:52 ` [PATCH v2 22/35] mtd: spi-nor: core: Use common naming scheme for setting mtd_info fields Tudor Ambarus
2021-08-17 16:26 ` Pratyush Yadav
2021-10-22 11:57 ` Michael Walle
2021-10-22 12:51 ` Tudor.Ambarus
2021-10-22 13:08 ` Michael Walle
2021-10-22 13:34 ` Tudor.Ambarus
2021-07-27 4:52 ` [PATCH v2 23/35] mtd: spi-nor: Get rid of nor->page_size Tudor Ambarus
2021-08-17 16:33 ` Pratyush Yadav
2021-10-22 12:01 ` Michael Walle
2021-07-27 4:52 ` [PATCH v2 24/35] mtd: spi-nor: core: Fix spi_nor_flash_parameter otp description Tudor Ambarus
2021-08-17 16:47 ` Pratyush Yadav
2021-10-22 12:07 ` Michael Walle
2021-07-27 4:52 ` [PATCH v2 25/35] mtd: spi-nor: core: Move spi_nor_set_addr_width() in spi_nor_setup() Tudor Ambarus
2021-08-17 16:52 ` Pratyush Yadav
2021-10-22 12:12 ` Michael Walle
2021-10-22 12:36 ` Tudor.Ambarus
2021-07-27 4:52 ` [PATCH v2 26/35] mtd: spi-nor: core: Introduce spi_nor_init_default_params() Tudor Ambarus
2021-08-24 17:30 ` Pratyush Yadav
2021-10-04 4:17 ` Tudor.Ambarus
2021-10-22 12:41 ` Michael Walle
2021-10-22 12:55 ` Tudor.Ambarus
2021-07-27 4:52 ` [PATCH v2 27/35] mtd: spi-nor: core: Init flash params based on SFDP first for new flash additions Tudor Ambarus
2021-08-24 17:51 ` Pratyush Yadav
2021-10-04 5:01 ` Tudor.Ambarus
2021-10-04 11:36 ` Tudor.Ambarus
2021-07-27 4:52 ` [PATCH v2 28/35] mtd: spi-nor: sst: sst26vf064b: Use SPI_NOR_PARSE_SFDP Tudor Ambarus
2021-07-27 4:52 ` [PATCH v2 29/35] mtd: spi-nor: winbond: w25q256jvm: " Tudor Ambarus
2021-07-27 4:52 ` [PATCH v2 30/35] mtd: spi-nor: issi: is25lp256: " Tudor Ambarus
2021-07-27 4:52 ` [PATCH v2 31/35] mtd: spi-nor: spansion: s25fl256s0: Skip SFDP parsing Tudor Ambarus
2021-07-27 4:52 ` [PATCH v2 32/35] mtd: spi-nor: gigadevice: gd25q256: Use SPI_NOR_PARSE_SFDP Tudor Ambarus
2021-07-27 4:52 ` [PATCH v2 33/35] mtd: spi-nor: micron-st: n25q256a: " Tudor Ambarus
2021-07-27 4:52 ` [PATCH v2 34/35] mtd: spi-nor: macronix: mx25l25635e: " Tudor Ambarus
2021-07-27 4:52 ` [PATCH v2 35/35] docs: mtd: spi-nor: Add details about how to propose a new flash addition Tudor Ambarus
2021-07-27 7:22 ` Michael Walle
2021-07-27 8:09 ` Tudor.Ambarus
2021-07-27 8:49 ` Michael Walle
2021-08-24 17:58 ` Pratyush Yadav
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