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[149.13.158.142]) by smtp.gmail.com with ESMTPSA id rk9sm4731852ejb.31.2021.10.15.13.05.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Oct 2021 13:05:44 -0700 (PDT) Date: Fri, 15 Oct 2021 22:05:41 +0200 From: Michael Trimarchi To: Miquel Raynal Cc: Greg Ungerer , Boris Brezillon , Sascha Hauer , Boris Brezillon , linux-mtd@lists.infradead.org Subject: Re: GPMI iMX6ull timeout on DMA Message-ID: <20211015200541.GA55401@panicking> References: <00b31833-69ba-42c5-57c9-37fa1f70efc5@kernel.org> <20190812093129.75888dad@collabora.com> <2e9e1f1c-ee57-425d-1791-70c66de52637@kernel.org> <20210201151335.210af8ca@xps13> <20210201161433.0c4ff0e3@xps13> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210201161433.0c4ff0e3@xps13> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211015_130548_798103_92344119 X-CRM114-Status: GOOD ( 45.45 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org Hi On Mon, Feb 01, 2021 at 04:14:33PM +0100, Miquel Raynal wrote: > Hi Michael, > = > Michael Nazzareno Trimarchi wrote on > Mon, 1 Feb 2021 16:08:23 +0100: > = > > Hi > > = > > On Mon, Feb 1, 2021 at 3:32 PM Michael Nazzareno Trimarchi > > wrote: > > > > > > Hi > > > > > > On Mon, Feb 1, 2021 at 3:13 PM Miquel Raynal wrote: = > > > > > > > > Hi Michael, > > > > > > > > Michael Nazzareno Trimarchi wrote on > > > > Sat, 30 Jan 2021 10:41:29 +0100: > > > > = > > > > > Hi Miquel > > > > > > > > > > commit f8e6ad14388067f91b26d044185d95623fbc9535 > > > > > Author: Michael Trimarchi > > > > > Date: Fri Jan 29 08:46:53 2021 +0100 > > > > > > > > > > mtd: nand: Calculate the clock before enable it > > > > > > > > > > Signed-off-by: Michael Trimarchi > > > > > Change-Id: I79b0da39de0a9b32ea0b002fa200d7f44d4f8ce7 > > > > > > > > > > diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c > > > > > b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c > > > > > index 322a008290e5..0bca52b3bc8f 100644 > > > > > --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c > > > > > +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c > > > > > @@ -377,6 +377,7 @@ static void gpmi_nfc_compute_timings(struct > > > > > gpmi_nand_data *this, > > > > > const struct nand_sdr_timing= s *sdr) > > > > > { > > > > > struct gpmi_nfc_hardware_timing *hw =3D &this->hw; > > > > > + struct resources *r =3D &this->resources; > > > > > unsigned int dll_threshold_ps =3D this->devdata->max_chai= n_delay; > > > > > unsigned int period_ps, reference_period_ps; > > > > > unsigned int data_setup_cycles, data_hold_cycles, addr_se= tup_cycles; > > > > > @@ -440,6 +441,8 @@ static void gpmi_nfc_compute_timings(struct > > > > > gpmi_nand_data *this, > > > > > hw->ctrl1n |=3D BF_GPMI_CTRL1_RDN_DELAY(sample_de= lay_factor) | > > > > > BM_GPMI_CTRL1_DLL_ENABLE | > > > > > (use_half_period ? BM_GPMI_CTRL1_HA= LF_PERIOD : 0); > > > > > + > > > > > + clk_set_rate(r->clock[0], hw->clk_rate); > > > > > } > > > > > > > > > > void gpmi_nfc_apply_timings(struct gpmi_nand_data *this) > > > > > @@ -449,8 +452,6 @@ void gpmi_nfc_apply_timings(struct gpmi_nand_= data *this) > > > > > void __iomem *gpmi_regs =3D r->gpmi_regs; > > > > > unsigned int dll_wait_time_us; > > > > > > > > > > - clk_set_rate(r->clock[0], hw->clk_rate); > > > > > - > > > > > writel(hw->timing0, gpmi_regs + HW_GPMI_TIMING0); > > > > > writel(hw->timing1, gpmi_regs + HW_GPMI_TIMING1); > > > > > > > > > > Right now I have this change applied and seems fine. That is the = only > > > > > difference I get. Clock is apply a bit earlier that when is enabl= ed > > > > > it. = > > > > > > > > This is very interesting. So this would mean the issue you are > > > > experiencing comes from the clock driver which kind of returns too > > > > early from clk_set_rate()? Could you report this to the clk ML/NXP = clk > > > > maintainers and keep us in copy? If it is as global as it sounds, we > > > > might not be the only ones affected. > > > > = > > > > > > The imx28 is broken too, so it's a general problem. I need to trace i= t down > > > I have a reverting for lts but it\s not the way to go > > > = > > = > > For imx28 you ask to set the rate to 22Mhz but you don't care about the= clock > > that you get back. You get back 12Mhz because the base clock is 24 Mhz = and seems > > that it can not get the point. You need to check if the clock > > requested is in range or ask > > for set_rate_clk_min to avoid to have somenthing lower. Then for > > imx6ull because is sporadic > > I think that is more connected to the clk_set_rate and when you change > > the register. Can not be a > > setting time? > = > So, if I understand correctly, we face two different problems: > - imx6*: seems like a clock issue regarding the clock settlement > - imx28: actual NAND driver issue (does not check the validity of the > new frequency). This should be handled properly in > ->setup_interface(). > Somenthing like this? Not compile/tested diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/= raw/gpmi-nand/gpmi-nand.c index 4d08e4ab5c1b..cc8146ab1b78 100644 --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c @@ -644,7 +644,7 @@ static int bch_set_geometry(struct gpmi_nand_data *this) * RDN_DELAY =3D ----------------------- {3} * RP */ -static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this, +static int gpmi_nfc_compute_timings(struct gpmi_nand_data *this, const struct nand_sdr_timings *sdr) { struct gpmi_nfc_hardware_timing *hw =3D &this->hw; @@ -656,6 +656,7 @@ static void gpmi_nfc_compute_timings(struct gpmi_nand_d= ata *this, int sample_delay_ps, sample_delay_factor; u16 busy_timeout_cycles; u8 wrn_dly_sel; + long clk_rate; = if (sdr->tRC_min >=3D 30000) { /* ONFI non-EDO modes [0-3] */ @@ -671,6 +672,10 @@ static void gpmi_nfc_compute_timings(struct gpmi_nand_= data *this, wrn_dly_sel =3D BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; } = + clk_rate =3D clk_round_rate(r->clock[0], hw->clk_rate); + if (clk_rate < hw->clk_rate || clk_rate <=3D 0) + return -ENOTSUPP; + /* SDR core timings are given in picoseconds */ period_ps =3D div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate); = @@ -746,6 +751,7 @@ static int gpmi_setup_interface(struct nand_chip *chip,= int chipnr, { struct gpmi_nand_data *this =3D nand_get_controller_data(chip); const struct nand_sdr_timings *sdr; + int ret =3D 0; = /* Retrieve required NAND timings */ sdr =3D nand_get_sdr_timings(conf); @@ -761,11 +767,11 @@ static int gpmi_setup_interface(struct nand_chip *chi= p, int chipnr, return 0; = /* Do the actual derivation of the controller timings */ - gpmi_nfc_compute_timings(this, sdr); - - this->hw.must_apply_timings =3D true; + ret =3D gpmi_nfc_compute_timings(this, sdr); + if (!ret) + this->hw.must_apply_timings =3D true; = - return 0; + return ret; } = /* Clears a BCH interrupt. */ > Thanks, > Miqu=E8l ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/