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Wed, 20 Oct 2021 06:59:16 -0500 Date: Wed, 20 Oct 2021 17:29:15 +0530 From: Pratyush Yadav To: Boris Brezillon CC: Mika Westerberg , Tudor Ambarus , Mark Brown , Lee Jones , Michael Walle , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Mauro Lima , Alexander Sverdlin , Andy Shevchenko , , Subject: Re: [PATCH v3 2/3] mtd: spi-nor: intel-spi: Convert to SPI MEM Message-ID: <20211020115913.uzo3ogkmrltnb26y@ti.com> References: <20211013114432.31352-1-mika.westerberg@linux.intel.com> <20211013114432.31352-3-mika.westerberg@linux.intel.com> <20211020114153.0f99c5df@collabora.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20211020114153.0f99c5df@collabora.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_045927_022669_639B89DD X-CRM114-Status: GOOD ( 22.60 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org On 20/10/21 11:41AM, Boris Brezillon wrote: > On Wed, 13 Oct 2021 14:44:31 +0300 > Mika Westerberg wrote: > > > The preferred way to implement SPI-NOR controller drivers is through SPI > > subsubsystem utilizing the SPI MEM core functions. This converts the > > Intel SPI flash controller driver over the SPI MEM by moving the driver > > from SPI-NOR subsystem to SPI subsystem and in one go make it use the > > SPI MEM functions. The driver name will be changed from intel-spi to > > spi-intel to match the convention used in the SPI subsystem. > > > > I skimmed over the driver changes, and I'm skeptical about this "let's > convert all spi-nor controller drivers into spi-mem drivers even if > they don't fit the spi-mem model" strategy. Clearly, the intel > controller is much more limited than any other spi-mem controller (I > mean feature-wise not perf-wise of course). The fact that you have to > check the opcode to decide whether the operation is supported or not, > or the way you deduce when to issue an erase vs a regular read/write is > kind of hack-ish. Not saying we shouldn't support this case in spi-mem, > but it should at least be done in a more controlled way. Maybe with an > explicit array of supported spi_mem operations, and driver specific > hooks for each of these operations so anything falling outside is > clearly identified and rejected (we have this sort of things in the raw > NAND framework). I am curious about how we can solve this. Any pointers to functions/drivers in raw NAND framework that follow this model? [...] -- Regards, Pratyush Yadav Texas Instruments Inc. ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/