From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
Cc: <broonie@kernel.org>, <benliang.zhao@mediatek.com>,
<dandan.he@mediatek.com>, <guochun.mao@mediatek.com>,
<bin.zhang@mediatek.com>, <sanny.chen@mediatek.com>,
<mao.zhong@mediatek.com>, <yingjoe.chen@mediatek.com>,
<donghunt@amazon.com>, <rdlee@amazon.com>,
<linux-mtd@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>
Subject: Re: [RFC,v3 4/5] arm64: dts: add snfi node for spi nand
Date: Tue, 9 Nov 2021 12:35:21 +0100 [thread overview]
Message-ID: <20211109123521.7785b8c3@xps13> (raw)
In-Reply-To: <20211022024021.14665-5-xiangsheng.hou@mediatek.com>
Hi Xiangsheng,
xiangsheng.hou@mediatek.com wrote on Fri, 22 Oct 2021 10:40:20 +0800:
> Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
You miss a commit message otherwise the content looks good to me.
> ---
> arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 18 ++++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt7622.dtsi | 13 +++++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
> index f2dc850010f1..f4ba86c451fc 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
> @@ -223,6 +223,24 @@ &nandc {
> status = "disabled";
> };
>
> +&snfi {
> + pinctrl-names = "default";
> + /* pin shared with spic */
> + pinctrl-0 = <&snfi_pins>;
> + nand-ecc-engine = <&bch>;
> + status = "disabled";
> +
> + spi_nand@0 {
> + compatible = "spi-nand";
> + reg = <0>;
> + spi-max-frequency = <104000000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + nand-ecc-engine = <&snfi>;
> + nand-ecc-placement = "interleaved";
> + };
> +};
> +
> &nor_flash {
> pinctrl-names = "default";
> pinctrl-0 = <&spi_nor_pins>;
> diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> index 890a942ec608..0525e4de5ec0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> @@ -545,6 +545,19 @@ nandc: nfi@1100d000 {
> status = "disabled";
> };
>
> + snfi: spi@1100d000 {
> + compatible = "mediatek,mt7622-snfi";
> + reg = <0 0x1100D000 0 0x1000>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg_ao CK_INFRA_NFI1_CK>,
> + <&infracfg_ao CK_INFRA_SPINFI1_CK>,
> + <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
> + clock-names = "nfi_clk", "snfi_clk", "hclk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> bch: ecc@1100e000 {
> compatible = "mediatek,mt7622-ecc";
> reg = <0 0x1100e000 0 0x1000>;
Thanks,
Miquèl
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next prev parent reply other threads:[~2021-11-09 11:36 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-22 2:40 [RFC,v3 0/5] Add driver for Mediatek SPI Nand and HW ECC controller Xiangsheng Hou
2021-10-22 2:40 ` [RFC,v3 1/5] mtd: ecc: move mediatek HW ECC driver Xiangsheng Hou
2021-11-09 11:22 ` Miquel Raynal
2021-10-22 2:40 ` [RFC,v3 2/5] mtd: ecc: realize Mediatek " Xiangsheng Hou
2021-11-09 12:18 ` Miquel Raynal
2021-11-12 8:40 ` xiangsheng.hou
2021-11-22 8:57 ` Miquel Raynal
2021-10-22 2:40 ` [RFC,v3 3/5] spi: add Mediatek SPI Nand controller driver Xiangsheng Hou
2021-11-09 11:46 ` Miquel Raynal
2021-11-12 8:40 ` xiangsheng.hou
2021-11-22 8:53 ` Miquel Raynal
2021-10-22 2:40 ` [RFC,v3 4/5] arm64: dts: add snfi node for spi nand Xiangsheng Hou
2021-11-09 11:35 ` Miquel Raynal [this message]
2021-10-22 2:40 ` [RFC, v3 5/5] mtd: spinand: skip set/get oob data bytes when interleaved case Xiangsheng Hou
2021-11-09 12:05 ` [RFC,v3 " Miquel Raynal
2021-11-12 8:33 ` xiangsheng.hou
2021-11-22 9:01 ` Miquel Raynal
2021-11-26 8:51 ` xiangsheng.hou
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