From: Herve Codina <herve.codina@bootlin.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>
Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
Herve Codina <herve.codina@bootlin.com>,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: [PATCH 2/4] mtd: rawnand: fsmc: Force to use 8 bits access when expected
Date: Fri, 12 Nov 2021 15:38:53 +0100 [thread overview]
Message-ID: <20211112143855.2678989-3-herve.codina@bootlin.com> (raw)
In-Reply-To: <20211112143855.2678989-1-herve.codina@bootlin.com>
Some data transfers are expected on 8 bits by the nand core.
The fsmc driver did not check this constraint and these transfers
can be done on 32 bits depending on buffer alignment and transfers
data size.
This patch ensures that these transfers will be 8bits transfers in
all cases.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
drivers/mtd/nand/raw/fsmc_nand.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
index 658f0cbe7ce8..7f057cfee6c4 100644
--- a/drivers/mtd/nand/raw/fsmc_nand.c
+++ b/drivers/mtd/nand/raw/fsmc_nand.c
@@ -540,12 +540,12 @@ static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
* @len: number of bytes to write
*/
static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf,
- int len)
+ int len, bool force_8bit)
{
int i;
if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
- IS_ALIGNED(len, sizeof(u32))) {
+ IS_ALIGNED(len, sizeof(u32)) && !force_8bit) {
u32 *p = (u32 *)buf;
len = len >> 2;
@@ -563,12 +563,13 @@ static void fsmc_write_buf(struct fsmc_nand_data *host, const u8 *buf,
* @buf: buffer to store date
* @len: number of bytes to read
*/
-static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len)
+static void fsmc_read_buf(struct fsmc_nand_data *host, u8 *buf, int len,
+ bool force_8bit)
{
int i;
if (IS_ALIGNED((uintptr_t)buf, sizeof(u32)) &&
- IS_ALIGNED(len, sizeof(u32))) {
+ IS_ALIGNED(len, sizeof(u32)) && !force_8bit) {
u32 *p = (u32 *)buf;
len = len >> 2;
@@ -646,7 +647,8 @@ static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
instr->ctx.data.len);
else
fsmc_read_buf(host, instr->ctx.data.buf.in,
- instr->ctx.data.len);
+ instr->ctx.data.len,
+ instr->ctx.data.force_8bit);
break;
case NAND_OP_DATA_OUT_INSTR:
@@ -656,7 +658,8 @@ static int fsmc_exec_op(struct nand_chip *chip, const struct nand_operation *op,
instr->ctx.data.len);
else
fsmc_write_buf(host, instr->ctx.data.buf.out,
- instr->ctx.data.len);
+ instr->ctx.data.len,
+ instr->ctx.data.force_8bit);
break;
case NAND_OP_WAITRDY_INSTR:
--
2.31.1
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next prev parent reply other threads:[~2021-11-12 14:53 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-12 14:38 [PATCH 0/4] mtd: rawnand: Fixes nand infra delay setting and FSMC nand controller Herve Codina
2021-11-12 14:38 ` [PATCH 1/4] mtd: rawnand: Fix nand_erase_op delay Herve Codina
2021-11-12 14:38 ` Herve Codina [this message]
2021-11-12 15:38 ` [PATCH 2/4] mtd: rawnand: fsmc: Force to use 8 bits access when expected Miquel Raynal
2021-11-17 13:47 ` Herve Codina
2021-11-12 14:38 ` [PATCH 3/4] mtd: rawnand: fsmc: Take instruction delay into account Herve Codina
2021-11-12 14:38 ` [PATCH 4/4] mtd: rawnand: fsmc: Fix timing computation Herve Codina
2021-11-12 15:52 ` Miquel Raynal
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