[PATCH v3 0/3] Stacked/parallel memories bindings

Miquel Raynal
2021-12-06T10:00:15Z

Hello Rob, Mark, Tudor & Pratyush,

Here is a third versions for these bindings, which applies on top of
Pratyush's work:
https://lore.kernel.org/all/20211109181911.2251-1-p.yadav@ti.com/

Cheers,
Miquèl

Changes in v3:
* Rebased on top of Pratyush's recent changes.
* Dropped the commit allowing to provide two reg entries on the node
name.
* Dropped the commit referencing spi-controller.yaml from
jedec,spi-nor.yaml, now replaced by spi-peripheral-props.yaml and
already done in Pratyush's series.
* Added Rob's Ack.
* Enhanced a commit message.
* Moved the new properties to the new SPI peripheral binding file.

Changes in v2:
* Dropped the dtc changes for now.
* Moved the properties in the device's nodes, not the controller's.
* Dropped the useless #address-cells change.
* Added a missing "minItems".
* Moved the new properties in the spi-controller.yaml file.
* Added an example using two stacked memories in the
spi-controller.yaml file.
* Renamed the properties to drop the Xilinx prefix.
* Added a patch to fix the spi-nor jedec yaml file.

Miquel Raynal (3):
dt-bindings: mtd: spi-nor: Allow two CS per device
spi: dt-bindings: Describe stacked/parallel memories modes
spi: dt-bindings: Add an example with two stacked flashes

.../bindings/mtd/jedec,spi-nor.yaml | 3 ++-
.../bindings/spi/spi-controller.yaml | 7 +++++++
.../bindings/spi/spi-peripheral-props.yaml | 21 +++++++++++++++++++
3 files changed, 30 insertions(+), 1 deletion(-)

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2.27.0