From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E456EC4332F for ; Thu, 9 Dec 2021 17:22:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LyQQkOHSul/I+e9XNX+qndF62FZDjDwDrC/AjZ0v2pA=; b=mHmsKQA87BUH7O 1MsXEq1tmYN7SbFjpYOFk6rMPboKcVOekp9eST/TDzASM7lDb/YtaD7BLWTiq9prmvy2vQOzlVsLM Uaiwex/qF0VAEapRnghWSG8h56MdGnY+c7CRSG4ZdRn9MLdP0hD3hc2Fqu4wvy6qzE9JZMmcME3j1 X3Hh+YsxDhV1SqXel/x2RSLYx3PnkN7q9lYpg69RE/75URhdBVwEGdySn9oTkbNE2L1gqXvXt97Di a5GLmh2YXj9hJCPpIdS9EefQeN+NBM38Nr4R1nSGnVJ09EW8+mYKTxz6D+B/GdtH1UC3oBl5MwVmL M9d7HBK9oHGYoFWE+GtQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvN6t-00GwJ8-HV; Thu, 09 Dec 2021 17:21:35 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mvN6d-00GwFc-Jd for linux-mtd@lists.infradead.org; Thu, 09 Dec 2021 17:21:21 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1639070479; x=1670606479; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G9E8VcyeLS5896oQypU6qg4HB08aR/RGLLu/CKuQpHg=; b=yFa1cmpi7g7cDwOIiENbnYQ1Ok4zlLkLxYv88HWsou/lODofv/+2bTMb sYyVgkcvJ2GJWPwyligTVnzMMalk3Tup054nwJbh1X9cQJbxJkRSaxCeC YtES4gwZgGsRmFesjvF6r2uqn9I/cxK4ntdBfsVrPgScalmFPItBG/1/s +mwPJjohwG+KmBOxyl7b6V0T6kYQX043NZ9WBMIYX0YaNvQDjQXZkzBhp qvFgy1tNFCaIvpAFY3w/WXo62HlRYTiSI4ajIfv3QwOCkthFJskXyH8Pv 8+6niyKzfyi/k3lFrXzn2PSjp2P0NR/53C888/6e+oYgV/BdY9orBPeCe Q==; IronPort-SDR: R0+AMwMzSLxa9qEzhniwginoElvAZDp87OvNWB2aWYDnOiUmMfrc+q2ZDoZheAuHGxJDiegzWJ 3FprPdmSIymF4TuhRtZlYi0tu4ZuSXrHkDZy7u0jkitV5J0ydciWHEee1QTCMXU2cfDe2bnY9e xlh1cxiKEsG85aKdP+dq4eG2aQWYP3WZ8izrYmqOZ//SvB+LBsmewlrJ7MM73epiNDCwfgWcV9 WUcB0qUpNAB5ObuN4DpQo4GZ4InkB8aPBua93sVOsqfYboZWmaPbAWQ5AYAp/XM5cZt2liMasg ka/5qpRerXbV255EdOXvlR2g X-IronPort-AV: E=Sophos;i="5.88,193,1635231600"; d="scan'208";a="79051485" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 Dec 2021 10:21:17 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 9 Dec 2021 10:21:17 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 9 Dec 2021 10:21:14 -0700 From: Tudor Ambarus To: , CC: , , , , , , , , Tudor Ambarus Subject: [PATCH 2/2] mtd: spi-nor: macronix: Add support for mx66lm1g45g Date: Thu, 9 Dec 2021 19:21:08 +0200 Message-ID: <20211209172109.398258-2-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211209172109.398258-1-tudor.ambarus@microchip.com> References: <20211209172109.398258-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211209_092119_733460_D283C818 X-CRM114-Status: GOOD ( 16.74 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org mx66lm1g45g supports just 1-1-1, 8-8-8 and 8d-8d-8d modes. There are versions of mx66lm1g45g which do not support SFDP, thus use SPI_NOR_SKIP_SFDP. The RDID command issued through the octal peripheral interface outputs data always in STR mode for whatever reason. Since 8d-8d-8s is not common, avoid reading the ID when enabling the octal dtr mode. Instead, read back the CR2 to check if the switch was successful. Tested in 1-1-1 and 8d-8d-8d modes using sama7g5 QSPI IP. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/macronix.c | 113 +++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 67aaa83038b6..1087504c52ca 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -32,6 +32,112 @@ static struct spi_nor_fixups mx25l25635_fixups = { .post_bfpt = mx25l25635_post_bfpt_fixups, }; +#define SPINOR_OP_READ_CR2 0x71 +#define SPINOR_OP_WRITE_CR2 0x72 +#define SPINOR_OP_MX_DTR_RD 0xee + +#define SPINOR_REG_CR2_MODE_ADDR 0 +#define SPINOR_REG_CR2_DTR_OPI_ENABLE BIT(1) +#define SPINOR_REG_CR2_SPI 0 + +#define SPINOR_REG_CR2_DUMMY_ADDR 0x300 +#define SPINOR_REG_CR2_DUMMY_20 0 + +static int spi_nor_macronix_octal_dtr_enable(struct spi_nor *nor, bool enable) +{ + struct spi_mem_op op; + int ret; + + /* Use 20 dummy cycles for memory array reads. */ + if (enable) { + nor->bouncebuf[0] = SPINOR_REG_CR2_DUMMY_20; + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRITE_CR2, 1), + SPI_MEM_OP_ADDR(4, SPINOR_REG_CR2_DUMMY_ADDR, + 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); + + ret = spi_nor_write_enable(nor); + if (ret) + return ret; + + ret = spi_mem_exec_op(nor->spimem, &op); + if (ret) + return ret; + + ret = spi_nor_wait_till_ready(nor); + if (ret) + return ret; + } + + /* Set/unset the octal and DTR enable bits. */ + if (enable) + nor->bouncebuf[0] = SPINOR_REG_CR2_DTR_OPI_ENABLE; + else + nor->bouncebuf[0] = SPINOR_REG_CR2_SPI; + + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRITE_CR2, 1), + SPI_MEM_OP_ADDR(4, SPINOR_REG_CR2_MODE_ADDR, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); + if (!enable) + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + + ret = spi_nor_write_enable(nor); + if (ret) + return ret; + + ret = spi_mem_exec_op(nor->spimem, &op); + if (ret) + return ret; + + /* Read back CR2 to make sure the switch was successful. */ + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_CR2, 1), + SPI_MEM_OP_ADDR(4, SPINOR_REG_CR2_MODE_ADDR, 1), + SPI_MEM_OP_DUMMY(enable ? 4 : 0, 1), + SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1)); + if (enable) + spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + + ret = spi_mem_exec_op(nor->spimem, &op); + if (ret) + return ret; + + if (enable) { + if (nor->bouncebuf[0] != SPINOR_REG_CR2_DTR_OPI_ENABLE) { + dev_dbg(nor->dev, "Failed to enable 8d-8d-8d mode.\n"); + return -EINVAL; + } + } else if (nor->bouncebuf[0] != SPINOR_REG_CR2_SPI) { + dev_dbg(nor->dev, "Failed to disable 8d-8d-8d mode.\n"); + return -EINVAL; + } + + return 0; +} + +static void mx66lm1g45g_late_init(struct spi_nor *nor) +{ + nor->params->octal_dtr_enable = spi_nor_macronix_octal_dtr_enable; + + /* Set the Fast Read settings. */ + nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR; + spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR], + 0, 20, SPINOR_OP_MX_DTR_RD, + SNOR_PROTO_8_8_8_DTR); + + nor->cmd_ext_type = SPI_NOR_EXT_INVERT; + nor->params->rdsr_dummy = 4; + nor->params->rdsr_addr_nbytes = 4; +} + +static struct spi_nor_fixups mx66lm1g45g_fixups = { + .late_init = mx66lm1g45g_late_init, +}; + static const struct flash_info macronix_parts[] = { /* Macronix */ { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1) @@ -100,6 +206,13 @@ static const struct flash_info macronix_parts[] = { { "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, + { "mx66lm1g45g", INFO(0xc2853b, 0, 64 * 1024, 2048) + NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SECT_4K | + SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP | + SPI_NOR_SOFT_RESET) + FIXUP_FLAGS(SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE) + .fixups = &mx66lm1g45g_fixups, + }, }; static void macronix_default_init(struct spi_nor *nor) -- 2.25.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/