Re: GPMC omap nand using CS1

[Miquel Raynal <miquel.raynal@bootlin.com>]

Hello Romain,

romain.naour@smile.fr wrote on Mon, 13 Dec 2021 11:18:03 +0100:

> Hello,
> 
> I'm using an AM3505 cpu with two nand device, nand0 use CS0 and nand1 use CS1.
> 
> The nand0 is ok but nand1 is not detected.
> I get "nand: No NAND device found"

Easy answer (support 101, sorry about that :-) ), did you check that the
CS was toggling with a scope? Just to be sure that this is a NAND
core/driver issue and not something else?

> Regarding the devicetree for nand1, I did something similar to omap3430-sdp.dts
> where the nand is on CS1.
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/arch/arm/boot/dts/omap3430-sdp.dts?h=v5.15.6#n102

And this is precisely the reason why we switched to a new
DT representation: as long as you have a single chip, not describing
the NAND device inside a bigger "nand" node was fine. But whenever we
need to support more than one it starts to be an issue. I saw that the
logic here was to add a second nand node which, on a pure DT
representation logic is wrong: the GPMC has subnodes which are the
different controller (there is only one NAND controller there) which
should contain two NAND device subnodes with their specific properties.
Anyway, that is not how this controller is currently being described,
so let's assume creating two NAND nodes is fine at least to make it
work.

I assume you tried:
* booting with only CS0 described -> works
* booting with only CS1 described -> No NAND device found error
Am I right?

> I'm not sure this dts actually works since in nand_base.c nand_detect() call
> nand_reset(chip, 0) with cs = 0.
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/mtd/nand/raw/nand_base.c?h=v5.15.6#n4945

This is indeed the first step, we always start with the first CS and
then if the first device was discovered, we check if the other CS are
wired. This only works of course if nand_scan() requests scanning more
than one CS. This is currently not the case and was already like that
for quite some time. Maybe that is why the NAND controller was
described twice in the link below, to get the probe of the controller
called twice?

Anyway if the question is 'how do I get CS1 being checked first', you
should look at the probe function which instantiate your controller.
That is where the driver is supposed to parse the DT, find the right
CS to handle and then register the NAND chip. From the core
perspective, it can use "target" 0, 1, etc, even though from the
controller perspective, target 0 for a given chip might be CS1. You can
look at "recent" drivers, like Marvell or Arasan which support several
CS.

> It seems it was possible to use two nand on gpmc (kernel 3.16):
> 
> https://e2e.ti.com/support/processors-group/processors/f/processors-forum/343017/am335x-gpmc-with-two-nand-flash-in-device-tree

I honestly do not know if this ever worked or if it was supported
upstream, it is very likely, looking at the current code base, that
if you want two CS on this board you are going to need to write a
couple of patches :)

Good luck, do not hesitate if you have other specific questions.

Thanks,
Miquèl

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