From: vincent@systemli.org
To: linux-mtd@lists.infradead.org
Cc: Nick Hainke <vincent@systemli.org>, David Bauer <mail@david-bauer.net>
Subject: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix
Date: Mon, 27 Dec 2021 10:16:38 +0100 [thread overview]
Message-ID: <20211227091638.177917-2-vincent@systemli.org> (raw)
In-Reply-To: <20211227091638.177917-1-vincent@systemli.org>
From: Nick Hainke <vincent@systemli.org>
Macronix flash chips seem to consist of only one status register.
These chips will not work with the "16-bit Write Status (01h) Command".
Disable SNOR_F_HAS_16BIT_SR for all Macronix chips.
Tested with MX25L6405D.
Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on
lock()/unlock()")
Signed-off-by: David Bauer <mail@david-bauer.net>
Signed-off-by: Nick Hainke <vincent@systemli.org>
---
drivers/mtd/spi-nor/macronix.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index f07b59a4120a..d530ab0b3b13 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -94,6 +94,7 @@ static void macronix_default_init(struct spi_nor *nor)
{
nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
+ nor->flags &= ~SNOR_F_HAS_16BIT_SR;
}
static const struct spi_nor_fixups macronix_fixups = {
--
2.34.1
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next prev parent reply other threads:[~2021-12-27 9:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-27 9:16 [PATCH 1/2] mtd: spi-nor: locking support for MX25L6405D vincent
2021-12-27 9:16 ` vincent [this message]
2021-12-29 14:08 ` [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix Tudor.Ambarus
2021-12-31 9:10 ` Nick
2021-12-31 9:50 ` Nick
2022-01-19 15:49 ` Michael Walle
2022-01-19 20:36 ` David Bauer
2022-01-20 8:08 ` Michael Walle
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