From: Samuel Holland <samuel@sholland.org>
To: Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>
Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
Samuel Holland <samuel@sholland.org>
Subject: [RFC PATCH 2/3] mtd: rawnand: Support non-power-of-two chip sizes
Date: Thu, 29 Dec 2022 13:09:04 -0600 [thread overview]
Message-ID: <20221229190906.6467-3-samuel@sholland.org> (raw)
In-Reply-To: <20221229190906.6467-1-samuel@sholland.org>
Some NAND chips have a number of pages that is not exactly a power of
two. Support this by calculating the shifts and masks for the next
larger power of two.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
drivers/mtd/nand/raw/nand_base.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index c3cc66039925..f46bad7796ed 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5003,6 +5003,7 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
u8 *id_data = chip->id.data;
u8 maf_id, dev_id;
u64 targetsize;
+ u32 chip_page_shift;
/*
* Let's start by initializing memorg fields that might be left
@@ -5148,18 +5149,13 @@ static int nand_detect(struct nand_chip *chip, struct nand_flash_dev *type)
chip->page_shift = ffs(mtd->writesize) - 1;
/* Convert chipsize to number of pages per chip -1 */
targetsize = nanddev_target_size(&chip->base);
- chip->pagemask = (targetsize >> chip->page_shift) - 1;
+ chip_page_shift = order_base_2(targetsize >> chip->page_shift);
+ chip->pagemask = BIT(chip_page_shift) - 1;
chip->bbt_erase_shift = chip->phys_erase_shift =
ffs(mtd->erasesize) - 1;
- if (targetsize & 0xffffffff)
- chip->chip_shift = ffs((unsigned)targetsize) - 1;
- else {
- chip->chip_shift = ffs((unsigned)(targetsize >> 32));
- chip->chip_shift += 32 - 1;
- }
-
- if (chip->chip_shift - chip->page_shift > 16)
+ chip->chip_shift = chip_page_shift + chip->page_shift;
+ if (chip_page_shift > 16)
chip->options |= NAND_ROW_ADDR_3;
chip->badblockbits = 8;
--
2.37.4
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next prev parent reply other threads:[~2022-12-29 19:27 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-29 19:09 [PATCH 0/3] mtd: rawnand: Add H27UCG8T2FTR-BC MLC NAND Samuel Holland
2022-12-29 19:09 ` [PATCH 1/3] mtd: rawnand: hynix: Add support for " Samuel Holland
2022-12-30 12:45 ` Miquel Raynal
2022-12-30 12:46 ` Miquel Raynal
2022-12-30 16:08 ` Samuel Holland
2023-01-02 10:06 ` Miquel Raynal
2023-01-02 15:50 ` Samuel Holland
2023-01-02 16:59 ` Miquel Raynal
2022-12-29 19:09 ` Samuel Holland [this message]
2022-12-29 19:09 ` [RFC PATCH 3/3] mtd: rawnand: hynix: Expose the full H27UCG8T2FTR-BC chip size Samuel Holland
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