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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Hector Palacios <hector.palacios@digi.com>
Cc: herve.codina@bootlin.com, linux-mtd@lists.infradead.org,
	sashal@kernel.org
Subject: Re: [PATCH v4] mtd: rawnand: hynix: fix up bit 0 of sdr_timing_mode
Date: Wed, 8 Mar 2023 16:38:30 +0100	[thread overview]
Message-ID: <20230308163830.55bb3378@xps-13> (raw)
In-Reply-To: <20230308142926.334787-1-hector.palacios@digi.com>

Hi Hector,

hector.palacios@digi.com wrote on Wed,  8 Mar 2023 15:29:26 +0100:

> According to the ONFI specification, bit 0 of 'SDR timing mode support'
> (bytes 129-130) "shall be 1". That means the NAND supports at least
> timing mode 0.
> 
> NAND chip Hynix H27U4G8F2GDA-BI (at least) is reading a 0 on this field
> which makes nand_choose_best_sdr_timings() return with error and the
> probe function to eventually fail.
> 
> Given that sdr_timing_modes bit 0 must be 1 by specification, force
> it in case the NAND reports it is not set. This is a safe assumption
> because the mode 0 is the minimum (safer) set of timings that the
> NAND can work with.
> 
> Signed-off-by: Hector Palacios <hector.palacios@digi.com>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Link: https://lore.kernel.org/linux-mtd/20230223165104.525852-1-hector.palacios@digi.com
> ---
> v4:
>   Fix bitwise operation on __le16 type, per sparse warning.

Sorry I had no time to answer your question, see below.

> v3:
>   Forcibly set bit 0.
> v2:
>   Move patch to Hynix specific fixup hook.
>   Use BIT(0) macro.
> v1:
>   Implement generic patch in nand_base.c.
> 
> 
>  drivers/mtd/nand/raw/nand_hynix.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/mtd/nand/raw/nand_hynix.c b/drivers/mtd/nand/raw/nand_hynix.c
> index 0d4d4bbfdece..c17cca316148 100644
> --- a/drivers/mtd/nand/raw/nand_hynix.c
> +++ b/drivers/mtd/nand/raw/nand_hynix.c
> @@ -728,8 +728,21 @@ static int hynix_nand_init(struct nand_chip *chip)
>  	return ret;
>  }
>  
> +static void hynix_fixup_onfi_param_page(struct nand_chip *chip,
> +					struct nand_onfi_params *p)
> +{
> +	/*
> +	 * Certain chips might report a 0 on sdr_timing_mode field
> +	 * (bytes 129-130). This has been seen on H27U4G8F2GDA-BI.
> +	 * According to ONFI specification, bit 0 of this field "shall be 1".
> +	 * Forcibly set this bit.
> +	 */
> +	p->sdr_timing_modes = cpu_to_le16(le16_to_cpu(p->sdr_timing_modes) | BIT(0));

Why not just:

	p->sdr_timing_modes |= cpu_to_le16(BIT(0));

?

> +}
> +
>  const struct nand_manufacturer_ops hynix_nand_manuf_ops = {
>  	.detect = hynix_nand_decode_id,
>  	.init = hynix_nand_init,
>  	.cleanup = hynix_nand_cleanup,
> +	.fixup_onfi_param_page = hynix_fixup_onfi_param_page,
>  };


Thanks,
Miquèl

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  reply	other threads:[~2023-03-08 15:39 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-08 14:29 [PATCH v4] mtd: rawnand: hynix: fix up bit 0 of sdr_timing_mode Hector Palacios
2023-03-08 15:38 ` Miquel Raynal [this message]
2023-03-10  8:02   ` Hector Palacios

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