Re: [PATCH v2 4/5] mtd: rawnand: qcom: Add support for read, write, erase exec_ops

Md Sadre Alam
2023-05-24T09:32:42Z

On 5/22/2023 7:23 PM, Miquel Raynal wrote:
>
> quic_mdalam@quicinc.com wrote on Thu, 11 May 2023 19:00:16 +0530:
>
>> This change will add exec_ops support for READ, WRITE, and ERASE
>> command.
>>
>> Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>> ---
>> Change in [v2]
>>
>> * Missed to post Cover-letter, so posting v2 patch with cover-letter
>>
>> drivers/mtd/nand/raw/qcom_nandc.c | 52 +++++++++++++++++++++++++++++--
>> 1 file changed, 49 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
>> index 8717d5086f80..14ab21a4771b 100644
>> --- a/drivers/mtd/nand/raw/qcom_nandc.c
>> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
>> @@ -1765,7 +1765,8 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
>> int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
>> int raw_cw = cw;
>>
>> - nand_read_page_op(chip, page, 0, NULL, 0);
>> + chip->cont_read.ongoing = false;
>
> This should be checked once for all by the core at startup, that's when
> you can tell the core continuous read is not supported by the
> controller.

Sure, Will fix this in next patch V3.
>
>> + nand_read_page_op(chip, page, 0, data_buf, mtd->writesize);
>> host->use_ecc = false;
>>
>> if (nandc->props->qpic_v2)
>> @@ -2182,14 +2183,24 @@ static void qcom_nandc_codeword_fixup(struct qcom_nand_host *host, int page)
>> static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf,
>> int oob_required, int page)
>> {
>> + struct mtd_info *mtd = nand_to_mtd(chip);
>> struct qcom_nand_host *host = to_qcom_nand_host(chip);
>> struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> + struct nand_ecc_ctrl *ecc = &chip->ecc;
>> u8 *data_buf, *oob_buf = NULL;
>>
>> if (host->nr_boot_partitions)
>> qcom_nandc_codeword_fixup(host, page);
>>
>> - nand_read_page_op(chip, page, 0, NULL, 0);
>> + chip->cont_read.ongoing = false;
>> + nand_read_page_op(chip, page, 0, buf, mtd->writesize);
>> + nandc->buf_count = 0;
>> + nandc->buf_start = 0;
>> + host->use_ecc = true;
>> + clear_read_regs(nandc);
>> + set_address(host, 0, page);
>> + update_rw_regs(host, ecc->steps, true, 0);
>> +
>> data_buf = buf;
>> oob_buf = oob_required ? chip->oob_poi : NULL;
>>
>> @@ -2259,6 +2270,10 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf,
>>
>> nand_prog_page_begin_op(chip, page, 0, NULL, 0);
>>
>> + set_address(host, 0, page);
>> + nandc->buf_count = 0;
>> + nandc->buf_start = 0;
>> +
>> clear_read_regs(nandc);
>> clear_bam_transaction(nandc);
>>
>> @@ -3081,7 +3096,38 @@ static int qcom_read_status_exec(struct nand_chip *chip,
>>
>> static int qcom_erase_cmd_type_exec(struct nand_chip *chip, const struct nand_subop *subop)
>> {
>> - return 0;
>> + struct qcom_nand_host *host = to_qcom_nand_host(chip);
>> + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> + struct qcom_op q_op;
>> + int ret = 0;
>> +
>> + qcom_parse_instructions(chip, subop, &q_op);
>> +
>> + q_op.cmd_reg |= PAGE_ACC | LAST_PAGE;
>> +
>> + pre_command(host, NAND_CMD_ERASE1);
>
> The instruction is up to the caller, not to the driver. If no other
> instruction rather than NAND_CMD_ERASE1 can be used with this pattern,
> then it should be properly described (see the Arasan controller,
> anfc_check_op()).
>
Thanks, will fix this in next patch V3.

>> +
>> + nandc_set_reg(chip, NAND_FLASH_CMD, q_op.cmd_reg);
>> + nandc_set_reg(chip, NAND_ADDR0, q_op.addr1_reg);
>> + nandc_set_reg(chip, NAND_ADDR1, q_op.addr2_reg);
>> + nandc_set_reg(chip, NAND_DEV0_CFG0,
>> + host->cfg0_raw & ~(7 << CW_PER_PAGE));
>> + nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw);
>> + nandc_set_reg(chip, NAND_EXEC_CMD, 1);
>> +
>> + write_reg_dma(nandc, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
>> + write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
>> + write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>> +
>> + ret = submit_descs(nandc);
>> + if (ret)
>> + dev_err(nandc->dev, "failure in sbumitting reset descriptor\n");
>> +
>> + free_descs(nandc);
>> +
>> + ret = qcom_wait_rdy_poll(chip, q_op.rdy_timeout_ms);
>> +
>> + return ret;
>> }
>>
>> static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_subop *subop)
>
>
> Thanks,
> Miquèl