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From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Michal Simek <michal.simek@amd.com>
Cc: Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>,
	Tudor Ambarus <tudor.ambarus@linaro.org>,
	Pratyush Yadav <pratyush@kernel.org>,
	Michael Walle <michael@walle.cc>, <linux-mtd@lists.infradead.org>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	<stable@vger.kernel.org>
Subject: Re: [PATCH 2/3] mtd: rawnand: arasan: Ensure program page operations are successful
Date: Tue, 12 Sep 2023 16:17:52 +0200	[thread overview]
Message-ID: <20230912161752.581019bc@xps-13> (raw)
In-Reply-To: <cf1a0b96-0f1e-4a6d-960b-93185faf27ba@amd.com>

Hi Michal,

michal.simek@amd.com wrote on Tue, 12 Sep 2023 15:55:23 +0200:

> Hi Miquel,
> 
> On 9/11/23 17:52, Miquel Raynal wrote:
> > Hi Michal,
> > 
> > miquel.raynal@bootlin.com wrote on Mon, 17 Jul 2023 21:42:20 +0200:
> >   
> >> The NAND core complies with the ONFI specification, which itself
> >> mentions that after any program or erase operation, a status check
> >> should be performed to see whether the operation was finished *and*
> >> successful.
> >>
> >> The NAND core offers helpers to finish a page write (sending the
> >> "PAGE PROG" command, waiting for the NAND chip to be ready again, and
> >> checking the operation status). But in some cases, advanced controller
> >> drivers might want to optimize this and craft their own page write
> >> helper to leverage additional hardware capabilities, thus not always
> >> using the core facilities.
> >>
> >> Some drivers, like this one, do not use the core helper to finish a page
> >> write because the final cycles are automatically managed by the
> >> hardware. In this case, the additional care must be taken to manually
> >> perform the final status check.
> >>
> >> Let's read the NAND chip status at the end of the page write helper and
> >> return -EIO upon error.
> >>
> >> Cc: Michal Simek <michal.simek@amd.com>
> >> Cc: stable@vger.kernel.org
> >> Fixes: 88ffef1b65cf ("mtd: rawnand: arasan: Support the hardware BCH ECC engine")
> >> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> >>
> >> ---
> >>
> >> Hello Michal,
> >>
> >> I have not tested this, but based on a report on another driver, I
> >> believe the status check is also missing here and could sometimes
> >> lead to unnoticed partial writes.
> >>
> >> Please test on your side that everything still works and let me
> >> know how it goes.  
> > 
> > Any news from the testing team about patches 2/3 and 3/3?  
> 
> I asked Amit to test and he didn't get back to me even I asked for it couple of times.

Ok.

> Can you please tell me how to test it? I will setup HW myself and test it and get back to you.

I believe setting up the board to use the hardware BCH engine and
performing basic erase/write/read testing with a known file and check
it still behaves correctly would work. You can also run

	nandbiterrs -i /dev/mtdx

as a second step and verify there is no difference with and without the
patch and finally check the impact:

	flash_speed -d -c 10 /dev/mtdx
	(be careful: this is a destructive operation)

Thanks,
Miquèl

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  reply	other threads:[~2023-09-12 14:18 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-17 19:42 [PATCH 1/3] mtd: rawnand: marvell: Ensure program page operations are successful Miquel Raynal
2023-07-17 19:42 ` [PATCH 2/3] mtd: rawnand: arasan: " Miquel Raynal
2023-09-11 15:52   ` Miquel Raynal
2023-09-12 13:55     ` Michal Simek
2023-09-12 14:17       ` Miquel Raynal [this message]
2023-09-20  7:55         ` Michal Simek
2023-09-21 10:25         ` Michal Simek
2023-09-22  9:14           ` Miquel Raynal
2023-09-22  9:16             ` Michal Simek
2023-09-22  9:17               ` Miquel Raynal
2023-09-22 14:51   ` Miquel Raynal
2023-07-17 19:42 ` [PATCH 3/3] mtd: rawnand: pl353: " Miquel Raynal
2023-09-22 14:51   ` Miquel Raynal
2023-08-26 13:33 ` [PATCH 1/3] mtd: rawnand: marvell: " Ravi Minnikanti
2023-09-11 15:53 ` Miquel Raynal

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