From: Miquel Raynal <miquel.raynal@bootlin.com>
To: "Usyskin, Alexander" <alexander.usyskin@intel.com>
Cc: Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Jani Nikula <jani.nikula@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
"Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
"Lubart, Vitaly" <vitaly.lubart@intel.com>,
"linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Winkler, Tomas" <tomas.winkler@intel.com>,
"De Marchi, Lucas" <lucas.demarchi@intel.com>
Subject: Re: [PATCH 06/10] drm/i915/spi: spi register with mtd
Date: Tue, 17 Oct 2023 16:46:15 +0200 [thread overview]
Message-ID: <20231017164615.5b58fcc6@xps-13> (raw)
In-Reply-To: <CY5PR11MB63663DB0C17321A1A0C46FF3EDD6A@CY5PR11MB6366.namprd11.prod.outlook.com>
Hi Alexander,
alexander.usyskin@intel.com wrote on Tue, 17 Oct 2023 14:20:32 +0000:
> > > > > + spi->mtd.writesize = SZ_1; /* 1 byte granularity */
> > > >
> > > > You say writesize should be aligned with 4 in your next patch?
> > >
> > > We support unaligned write by reading aligned 4bytes,
> > > replacing changed bytes there and writing whole 4bytes back.
> > > Is there any problem with this approach?
> >
> > Is there a reason to do that manually rather than letting the core
> > handle the complexity?
> >
> I was not aware that core can do this. The core implements above logic
> if I put SZ_4 here and caller try to write, say, one byte?
> And sync multiple writers?
> If so, I can remove manual work, I think, and make the patches smaller.
I haven't checked in detail but I would expect this yes. Please have a
round of tests and if it works, please simplify this part.
Thanks,
Miquèl
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next prev parent reply other threads:[~2023-10-17 14:46 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-10 12:39 [PATCH 00/10] drm/i915/spi: spi access for discrete graphics Alexander Usyskin
2023-09-10 12:39 ` [PATCH 01/10] drm/i915/spi: add spi device " Alexander Usyskin
2023-09-11 15:41 ` Jani Nikula
2023-09-12 10:47 ` Usyskin, Alexander
2023-09-10 12:39 ` [PATCH 02/10] drm/i915/spi: add intel_spi_region map Alexander Usyskin
2023-09-10 12:39 ` [PATCH 03/10] drm/i915/spi: add driver for on-die spi device Alexander Usyskin
2023-09-10 12:39 ` [PATCH 04/10] drm/i915/spi: implement region enumeration Alexander Usyskin
2023-09-10 12:39 ` [PATCH 05/10] drm/i915/spi: implement spi access functions Alexander Usyskin
2023-09-10 12:39 ` [PATCH 06/10] drm/i915/spi: spi register with mtd Alexander Usyskin
2023-10-16 8:39 ` Miquel Raynal
2023-10-17 11:54 ` Usyskin, Alexander
2023-10-17 13:55 ` Miquel Raynal
2023-10-17 14:20 ` Usyskin, Alexander
2023-10-17 14:46 ` Miquel Raynal [this message]
2023-11-14 8:47 ` Usyskin, Alexander
2023-11-14 9:13 ` Miquel Raynal
2024-02-14 12:16 ` Usyskin, Alexander
2024-02-19 9:09 ` Miquel Raynal
2023-09-10 12:39 ` [PATCH 07/10] drm/i915/spi: mtd: implement access handlers Alexander Usyskin
2023-09-10 12:39 ` [PATCH 08/10] drm/i915/spi: align 64bit read and write Alexander Usyskin
2023-09-10 12:39 ` [PATCH 09/10] drm/i915/spi: wake card on operations Alexander Usyskin
2023-09-10 12:39 ` [PATCH 10/10] drm/i915/spi: add support for access mode Alexander Usyskin
2023-09-11 7:42 ` [PATCH 00/10] drm/i915/spi: spi access for discrete graphics Miquel Raynal
2023-09-12 10:50 ` Usyskin, Alexander
2023-09-12 12:14 ` Mark Brown
2023-09-12 13:15 ` Usyskin, Alexander
2023-09-12 13:21 ` Miquel Raynal
2023-09-12 13:36 ` Mark Brown
2023-09-20 13:52 ` Usyskin, Alexander
2023-09-20 15:54 ` Mark Brown
2023-09-20 21:00 ` Winkler, Tomas
2023-09-21 11:29 ` Mark Brown
2023-09-27 14:11 ` Usyskin, Alexander
2023-09-27 14:37 ` Mark Brown
2023-09-27 14:54 ` Miquel Raynal
2023-09-28 6:33 ` Usyskin, Alexander
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