[PATCH 4/5] arm64: dts: imx8-ss-conn: add gpmi nand node

Frank Li
2024-05-17T18:11:08Z

Add gpmi nand support.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 69 +++++++++++++++++++++++++
1 file changed, 69 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 4aaf5a0c1ed8a..a4a10ce03bfe0 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -28,6 +28,13 @@ conn_ipg_clk: clock-conn-ipg {
clock-output-names = "conn_ipg_clk";
};

+conn_bch_clk: clock-conn-bch {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ clock-output-names = "conn_bch_clk";
+};
+
conn_subsys: bus@5b000000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -302,4 +309,66 @@ usb3_lpcg: clock-controller@5b280000 {
"usb3_aclk";
power-domains = <&pd IMX_SC_R_USB_2_PHY>;
};
+
+ rawnand_0_lpcg: clock-controller@5b290000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b290000 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>,
+ <&conn_axi_clk>,
+ <&conn_axi_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
+ clock-output-names = "gpmi_bch",
+ "gpmi_io",
+ "gpmi_apb",
+ "gpmi_bch_apb";
+ power-domains = <&pd IMX_SC_R_NAND>;
+ };
+
+ rawnand_4_lpcg: clock-controller@5b290004 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b290004 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&conn_axi_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "apbhdma_hclk";
+ power-domains = <&pd IMX_SC_R_NAND>;
+ };
+
+ dma_apbh: dma-controller@5b810000 {
+ compatible = "fsl,imx8qxp-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x5b810000 0x2000>;
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&rawnand_4_lpcg IMX_LPCG_CLK_0>;
+ power-domains = <&pd IMX_SC_R_NAND>;
+ };
+
+ gpmi: nand-controller@5b812000{
+ compatible = "fsl,imx8qxp-gpmi-nand";
+ reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>;
+ reg-names = "gpmi-nand", "bch";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&rawnand_0_lpcg IMX_LPCG_CLK_1>,
+ <&rawnand_0_lpcg IMX_LPCG_CLK_4>,
+ <&rawnand_0_lpcg IMX_LPCG_CLK_0>,
+ <&rawnand_0_lpcg IMX_LPCG_CLK_5>;
+ clock-names = "gpmi_io", "gpmi_apb",
+ "gpmi_bch", "gpmi_bch_apb";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ power-domains = <&pd IMX_SC_R_NAND>;
+ assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>;
+ assigned-clock-rates = <50000000>;
+ status = "disabled";
+ };
};

--
2.34.1