From: Brian Norris <computersforpeace@gmail.com>
To: linux-mtd@lists.infradead.org
Cc: Brian Norris <computersforpeace@gmail.com>,
Michael Walle <mwalle@kernel.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Pratyush Yadav <pratyush@kernel.org>,
Richard Weinberger <richard@nod.at>,
Tudor Ambarus <tudor.ambarus@linaro.org>,
Vignesh Raghavendra <vigneshr@ti.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH] mtd: spi-nor: micron-st: Add n25q064a WP support
Date: Fri, 26 Jul 2024 11:58:18 -0700 [thread overview]
Message-ID: <20240726185825.142733-1-computersforpeace@gmail.com> (raw)
These flash chips are used on Google / TP-Link / ASUS OnHub devices, and
OnHub devices are write-protected by default (same as any other
ChromeOS/Chromebook system). I've referred to datasheets, and tested on
OnHub devices.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
---
drivers/mtd/spi-nor/micron-st.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 3c6499fdb712..e6bab2d00c92 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -436,6 +436,8 @@ static const struct flash_info st_nor_parts[] = {
.id = SNOR_ID(0x20, 0xbb, 0x17),
.name = "n25q064a",
.size = SZ_8M,
+ .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6,
.no_sfdp_flags = SECT_4K | SPI_NOR_QUAD_READ,
}, {
.id = SNOR_ID(0x20, 0xbb, 0x18),
--
2.43.0
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next reply other threads:[~2024-07-26 18:58 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-26 18:58 Brian Norris [this message]
2024-07-30 6:51 ` [PATCH] mtd: spi-nor: micron-st: Add n25q064a WP support Michael Walle
2024-07-30 11:24 ` Pratyush Yadav
2024-07-30 11:33 ` Tudor Ambarus
2024-07-30 17:28 ` Brian Norris
2024-07-31 8:51 ` Tudor Ambarus
2024-07-31 9:05 ` Michael Walle
2024-07-31 17:31 ` Brian Norris
2024-08-05 9:01 ` Michael Walle
2024-07-31 17:10 ` Brian Norris
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