[PATCH v6 09/11] drm/i915/nvm: add support for access mode

Alexander Usyskin
2025-03-02T14:21:32Z

Check NVM access mode from GSC FW status registers
and overwrite access status read from SPI descriptor, if needed.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/intel_nvm.c | 25 ++++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_nvm.c b/drivers/gpu/drm/i915/intel_nvm.c
index 75d3ebe669ff..dd3999c934a7 100644
--- a/drivers/gpu/drm/i915/intel_nvm.c
+++ b/drivers/gpu/drm/i915/intel_nvm.c
@@ -10,6 +10,7 @@
#include "intel_nvm.h"

#define GEN12_GUNIT_NVM_SIZE 0x80
+#define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3)

static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] = {
[0] = { .name = "DESCRIPTOR", },
@@ -22,6 +23,28 @@ static void i915_nvm_release_dev(struct device *dev)
{
}

+static bool i915_nvm_writable_override(struct drm_i915_private *i915)
+{
+ resource_size_t base;
+ bool writable_override;
+
+ if (IS_DG1(i915)) {
+ base = DG1_GSC_HECI2_BASE;
+ } else if (IS_DG2(i915)) {
+ base = DG2_GSC_HECI2_BASE;
+ } else {
+ drm_err(&i915->drm, "Unknown platform\n");
+ return true;
+ }
+
+ writable_override =
+ !(intel_uncore_read(&i915->uncore, HECI_FWSTS(base, 2)) &
+ HECI_FW_STATUS_2_NVM_ACCESS_MODE);
+ if (writable_override)
+ drm_info(&i915->drm, "NVM access overridden by jumper\n");
+ return writable_override;
+}
+
void intel_nvm_init(struct drm_i915_private *i915)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
@@ -43,7 +66,7 @@ void intel_nvm_init(struct drm_i915_private *i915)

nvm = i915->nvm;

- nvm->writeable_override = true;
+ nvm->writable_override = i915_nvm_writable_override(i915);
nvm->bar.parent = &pdev->resource[0];
nvm->bar.start = GEN12_GUNIT_NVM_BASE + pdev->resource[0].start;
nvm->bar.end = nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1;
--
2.43.0