From: Gabor Juhos <j4g8y7@gmail.com>
To: Mark Brown <broonie@kernel.org>,
Manivannan Sadhasivam <mani@kernel.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>
Cc: Varadarajan Narayanan <quic_varada@quicinc.com>,
Md Sadre Alam <quic_mdalam@quicinc.com>,
Sricharan Ramabadhran <quic_srichara@quicinc.com>,
linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
Gabor Juhos <j4g8y7@gmail.com>
Subject: [PATCH v2 1/2] mtd: nand: qpic-common: add defines for ECC_MODE values
Date: Wed, 02 Jul 2025 14:35:23 +0200 [thread overview]
Message-ID: <20250702-qpic-snand-8bit-ecc-v2-1-ae2c17a30bb7@gmail.com> (raw)
In-Reply-To: <20250702-qpic-snand-8bit-ecc-v2-0-ae2c17a30bb7@gmail.com>
Add defines for the values of the ECC_MODE field of the NAND_DEV0_ECC_CFG
register and change both the 'qcom-nandc' and 'spi-qpic-snand' drivers to
use those instead of magic numbers.
No functional changes. This is in preparation for adding 8 bit ECC strength
support for the 'spi-qpic-snand' driver.
Reviewed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
---
Changes in v2:
- rebase on tip of spi/for-6.17
- add 'Reviewed-by' tag from Alam
---
drivers/mtd/nand/raw/qcom_nandc.c | 6 +++---
drivers/spi/spi-qpic-snand.c | 2 +-
include/linux/mtd/nand-qpic-common.h | 2 ++
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 1003cf118c01b8403c9a0f275f7fa1ba2ba597d6..4dd6f1a4e797857471ea57386dfed715f5b3019d 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -1379,7 +1379,7 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
int cwperpage, bad_block_byte, ret;
bool wide_bus;
- int ecc_mode = 1;
+ int ecc_mode = ECC_MODE_8BIT;
/* controller only supports 512 bytes data steps */
ecc->size = NANDC_STEP_SIZE;
@@ -1400,7 +1400,7 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
if (ecc->strength >= 8) {
/* 8 bit ECC defaults to BCH ECC on all platforms */
host->bch_enabled = true;
- ecc_mode = 1;
+ ecc_mode = ECC_MODE_8BIT;
if (wide_bus) {
host->ecc_bytes_hw = 14;
@@ -1420,7 +1420,7 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
if (nandc->props->ecc_modes & ECC_BCH_4BIT) {
/* BCH */
host->bch_enabled = true;
- ecc_mode = 0;
+ ecc_mode = ECC_MODE_4BIT;
if (wide_bus) {
host->ecc_bytes_hw = 8;
diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c
index ca55f9bcd17b4556ffd413c11d6d5aa900c67f85..7219bcaf4055aaa46ee1016ca9bc77aaeef191e4 100644
--- a/drivers/spi/spi-qpic-snand.c
+++ b/drivers/spi/spi-qpic-snand.c
@@ -343,7 +343,7 @@ static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
FIELD_PREP(ECC_SW_RESET, 0) |
FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
- FIELD_PREP(ECC_MODE_MASK, 0) |
+ FIELD_PREP(ECC_MODE_MASK, ECC_MODE_4BIT) |
FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203);
diff --git a/include/linux/mtd/nand-qpic-common.h b/include/linux/mtd/nand-qpic-common.h
index e8462deda6dbf61f99bbcb39e7cb12cdf66898fd..0d944db363cd249ad13cabcd6d0e1b4c7bc81d92 100644
--- a/include/linux/mtd/nand-qpic-common.h
+++ b/include/linux/mtd/nand-qpic-common.h
@@ -101,6 +101,8 @@
#define ECC_SW_RESET BIT(1)
#define ECC_MODE 4
#define ECC_MODE_MASK GENMASK(5, 4)
+#define ECC_MODE_4BIT 0
+#define ECC_MODE_8BIT 1
#define ECC_PARITY_SIZE_BYTES_BCH 8
#define ECC_PARITY_SIZE_BYTES_BCH_MASK GENMASK(12, 8)
#define ECC_NUM_DATA_BYTES 16
--
2.50.0
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next prev parent reply other threads:[~2025-07-02 13:51 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-02 12:35 [PATCH v2 0/2] spi: spi-qpic-snand: enable 8 bits ECC strength support Gabor Juhos
2025-07-02 12:35 ` Gabor Juhos [this message]
2025-07-02 15:57 ` [PATCH v2 1/2] mtd: nand: qpic-common: add defines for ECC_MODE values Miquel Raynal
2025-07-02 12:35 ` [PATCH v2 2/2] spi: spi-qpic-snand: add support for 8 bits ECC strength Gabor Juhos
2025-07-04 13:05 ` [PATCH v2 0/2] spi: spi-qpic-snand: enable 8 bits ECC strength support Mark Brown
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