From: Santhosh Kumar K <s-k6@ti.com>
To: <broonie@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
<conor+dt@kernel.org>, <miquel.raynal@bootlin.com>,
<richard@nod.at>, <vigneshr@ti.com>, <pratyush@kernel.org>,
<mwalle@kernel.org>, <takahiro.kuwano@infineon.com>
Cc: <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>,
<praneeth@ti.com>, <u-kumar1@ti.com>, <a-dutta@ti.com>,
<s-k6@ti.com>
Subject: [PATCH v7 04/18] spi: spi-mem: teach spi_mem_adjust_op_freq() about post-config ops
Date: Wed, 12 Aug 2026 00:02:59 +0530 [thread overview]
Message-ID: <20260811183313.1550425-5-s-k6@ti.com> (raw)
In-Reply-To: <20260811183313.1550425-1-s-k6@ti.com>
Extend spi_mem_adjust_op_freq() with a bypass for post-config ops:
when op->max_freq equals post_config_max_speed_hz (the value written by
execute_tuning on success), return immediately leaving op->max_freq
unchanged. All other ops are capped to max_speed_hz, the
always-reachable base rate. This places the policy at the single
existing frequency-adjustment point so exec_op(), supports_op(), and
calc_op_duration() all see consistent frequencies.
Also extend spi_mem_default_supports_op() to require per_op_freq
controller capability for post-config ops. A post-config op runs at a
different clock rate than the pre-config base; a controller that cannot
switch frequencies per-op cannot execute it correctly.
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
---
drivers/spi/spi-mem.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index a88b9f038356..c74858e58073 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -206,7 +206,8 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
return false;
if (op->max_freq &&
- op->max_freq < mem->spi->max_speed_hz) {
+ (op->max_freq < mem->spi->max_speed_hz ||
+ op->max_freq == mem->spi->post_config_max_speed_hz)) {
if (!spi_mem_controller_is_capable(ctlr, per_op_freq))
return false;
}
@@ -591,9 +592,18 @@ EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size);
* Some chips have per-op frequency limitations and must adapt the maximum
* speed. This function allows SPI mem drivers to set @op->max_freq to the
* maximum supported value.
+ *
+ * When @mem->spi->post_config_max_speed_hz is set, ops with @op->max_freq
+ * equal to that value are treated as post-configuration ops (e.g. PHY-tuned)
+ * and are allowed to run at the full post-config rate. All other ops are
+ * capped to @mem->spi->max_speed_hz, the always-reachable base rate.
*/
void spi_mem_adjust_op_freq(struct spi_mem *mem, struct spi_mem_op *op)
{
+ if (mem->spi->post_config_max_speed_hz &&
+ op->max_freq == mem->spi->post_config_max_speed_hz)
+ return;
+
if (!op->max_freq || op->max_freq > mem->spi->max_speed_hz)
op->max_freq = mem->spi->max_speed_hz;
}
--
2.34.1
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next prev parent reply other threads:[~2026-08-11 18:34 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-11 18:32 [PATCH v7 00/18] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-08-11 18:32 ` [PATCH v7 01/18] spi: dt-bindings: add spi-max-post-config-frequency-hz property Santhosh Kumar K
2026-08-11 18:32 ` [PATCH v7 02/18] spi: dt-bindings: add spi-phy-pattern-partition property Santhosh Kumar K
2026-08-11 18:32 ` [PATCH v7 03/18] spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz Santhosh Kumar K
2026-08-11 18:32 ` Santhosh Kumar K [this message]
2026-08-11 18:33 ` [PATCH v7 05/18] spi: spi-mem: add execute_tuning callback and spi_mem_execute_tuning() Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 06/18] spi: cadence-quadspi: move cqspi_readdata_capture earlier Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 07/18] spi: cadence-quadspi: add DQS support to read data capture Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 08/18] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 09/18] spi: cadence-quadspi: skip DDR PHY tuning for 2-byte-address ops (i2383) Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 10/18] spi: cadence-quadspi: refactor direct read path for PHY support Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 11/18] spi: cadence-quadspi: enable PHY for direct reads Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 12/18] spi: cadence-quadspi: enable PHY for indirect writes Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 13/18] spi: cadence-quadspi: reprogram CS timing on every chip-select switch Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 14/18] spi: cadence-quadspi: reprogram PHY DLL on runtime resume Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 15/18] mtd: spinand: extract variant ranking logic into spinand_op_find_best_variant() Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 16/18] mtd: spinand: negotiate optimal controller operating point before dirmap creation Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 17/18] mtd: spi-nor: extract read op template construction into helper Santhosh Kumar K
2026-08-11 18:33 ` [PATCH v7 18/18] mtd: spi-nor: run controller optimization before dirmap creation Santhosh Kumar K
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