From: Alexander Usyskin <alexander.usyskin@intel.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>
Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
Menachem Adin <menachem.adin@intel.com>,
stable@vger.kernel.org,
Alexander Usyskin <alexander.usyskin@intel.com>
Subject: [PATCH v2] mtd: mtd_intel_dg: reset poll counter for each erase
Date: Thu, 27 Aug 2026 08:11:56 +0300 [thread overview]
Message-ID: <20260827-mtd_eraze_to_fix-v2-1-1395ae4fb795@intel.com> (raw)
From: Menachem Adin <menachem.adin@intel.com>
The non-posted erase polling counter is initialized only once per MTD
erase request. Large requests therefore share the polling budget across
all 4K erase commands and can fail with -ETIME even though no individual
command timed out.
Reset the counter for each 4K erase command so every operation gets the
intended completion timeout.
Cc: stable@vger.kernel.org
Fixes: a1c940cbf505 ("drm/xe/nvm: add support for non-posted erase")
Signed-off-by: Menachem Adin <menachem.adin@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
Changes in v2:
- Add Fixes tag and stable cc
- Link to v1: https://lore.kernel.org/r/20260826-mtd_eraze_to_fix-v1-1-b8a893333075@intel.com
---
drivers/mtd/devices/mtd_intel_dg.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/mtd_intel_dg.c b/drivers/mtd/devices/mtd_intel_dg.c
index f2fa8f68d190..6e226c0c7f17 100644
--- a/drivers/mtd/devices/mtd_intel_dg.c
+++ b/drivers/mtd/devices/mtd_intel_dg.c
@@ -387,7 +387,7 @@ idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64 *fail_a
void __iomem *base2 = nvm->base2;
void __iomem *base = nvm->base;
const u32 block = 0x10;
- u32 iter = 0;
+ u32 iter;
u32 reg;
u64 i;
@@ -396,6 +396,7 @@ idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64 *fail_a
iowrite32(region << 24 | block, base + NVM_ERASE_REG);
if (nvm->non_posted_erase) {
/* Wait for Erase Done */
+ iter = 0;
reg = ioread32(base2 + NVM_DEBUG_REG);
while (!(reg & NVM_NON_POSTED_ERASE_DONE) &&
++iter < NVM_NON_POSTED_ERASE_DONE_ITER) {
---
base-commit: 8d3ae59288f1e7d58d76558a6ee96d533bc5019f
change-id: 20260826-mtd_eraze_to_fix-3708e0f99b1a
Best regards,
--
Alexander Usyskin <alexander.usyskin@intel.com>
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reply other threads:[~2026-08-27 5:12 UTC|newest]
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