Re: [Fwd: cfi_cmdset_0001.c: do_write_buffer bug]

Re: [Fwd: cfi_cmdset_0001.c: do_write_buffer bug]

[Andrey Filippov]

Working with Intel TE28F640J3A and Axis ETRAX100LX processor I ran over a bug in cfi_cmdset_0001.c: do_write_buffer. It checks ready state 20 times but does not resend 
Write-to-Buffer command (E8) before new checks. So if it was not ready first time it will never be ready later.

Andrey Filippov

Re: [Fwd: cfi_cmdset_0001.c: do_write_buffer bug]

[David Woodhouse]

andrey@elphel.com said:
> Working with Intel TE28F640J3A and Axis ETRAX100LX processor I ran
> over a bug in cfi_cmdset_0001.c: do_write_buffer. It checks ready
> state 20 times but does not resend  Write-to-Buffer command (E8)
> before new checks. So if it was not ready first time it will never be
> ready later.

Fixed in CVS. thanks. 

--
dwmw2

RE: [Fwd: cfi_cmdset_0001.c: do_write_buffer bug]

[John Hall]

On Sun 16/06/2002, Andrey Filippov <andrey@elphel.com> wrote:

> Working with Intel TE28F640J3A and Axis ETRAX100LX processor I ran
> over a bug in cfi_cmdset_0001.c: do_write_buffer. It checks ready
> state 20 times but does not resend Write-to-Buffer command (E8) before
> new checks. So if it was not ready first time it will never be ready
> later.

I was going to report exactly the same problem this morning. We have an
additional problem however. We currently have two Intel Strata Flash
parts in 16 bit mode to form a single 32 bit interface to a StrongARM
SA1110. We have found that sometimes, one chip returns ready, but the
second does not. You are then in a Catch-22 since you're supposed to
re-issue the write command to the one that's not ready but cannot to the
one that is ready.

Has anyone else come across this problem?

Regards,
John Hall

RE: [Fwd: cfi_cmdset_0001.c: do_write_buffer bug]

[Joakim Tjernlund]

Hi John

Have made any progress on this? I too have 2 Strata Flash in 16-bit mode to form a 32-bit
interface. I have yet to encounter this problem though.

  Jocke
> 
> On Sun 16/06/2002, Andrey Filippov <andrey@elphel.com> wrote:
> 
> > Working with Intel TE28F640J3A and Axis ETRAX100LX processor I ran
> > over a bug in cfi_cmdset_0001.c: do_write_buffer. It checks ready
> > state 20 times but does not resend Write-to-Buffer command (E8) before
> > new checks. So if it was not ready first time it will never be ready
> > later.
> 
> I was going to report exactly the same problem this morning. We have an
> additional problem however. We currently have two Intel Strata Flash
> parts in 16 bit mode to form a single 32 bit interface to a StrongARM
> SA1110. We have found that sometimes, one chip returns ready, but the
> second does not. You are then in a Catch-22 since you're supposed to
> re-issue the write command to the one that's not ready but cannot to the
> one that is ready.
> 
> Has anyone else come across this problem?
> 
> Regards,
> John Hall
> 
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
> 

RE: [Fwd: cfi_cmdset_0001.c: do_write_buffer bug]

[John Hall]

Joakim Tjernlund wrote:

> > I was going to report exactly the same problem this morning. We have
> > an additional problem however. We currently have two Intel Strata
> > Flash parts in 16 bit mode to form a single 32 bit interface to a
> > StrongARM SA1110. We have found that sometimes, one chip returns
> > ready, but the second does not. You are then in a Catch-22 since
> > you're supposed to re-issue the write command to the one that's not
> > ready but cannot to the one that is ready.

> Have made any progress on this? I too have 2 Strata Flash in 16-bit
> mode to form a 32-bit interface. I have yet to encounter this problem
> though.

Not yet. We've spoken to Intel and they acknowledge there might be a
problem, but we're waiting for them to get back to us.

john

Re: [Fwd: cfi_cmdset_0001.c: do_write_buffer bug]

[David Woodhouse]

John.Hall@optionexist.co.uk said:
>  Not yet. We've spoken to Intel and they acknowledge there might be a
> problem, but we're waiting for them to get back to us.

OK, I suspect what we want to do is something like...

 Send WriteToBuffer command.
 Poll for a little while for chips to become ready.
 If neither chip is ready, repeat.
 If only one chip is ready, abort the WriteToBuffer. Send a zero-length 
	(or one-byte) buffer and then something other than a WriteConfirm
	command, to abort the write. Clear the resulting 'Invalid Command/
	Sequence' error bits which will get set, and start again.

--
dwmw2

RE: [Fwd: cfi_cmdset_0001.c: do_write_buffer bug]

[John Hall]

On 20 June 2002 13:25 David Woodhouse <dwmw2@infradead.org> wrote:

> John.Hall@optionexist.co.uk said:
> >  Not yet. We've spoken to Intel and they acknowledge there might be
> >  a problem, but we're waiting for them to get back to us.

> OK, I suspect what we want to do is something like...
> 
>  Send WriteToBuffer command.
>  Poll for a little while for chips to become ready.
>  If neither chip is ready, repeat.
>  If only one chip is ready, abort the WriteToBuffer. Send a
>  zero-length (or one-byte) buffer and then something other than a
>  WriteConfirm command, to abort the write. Clear the resulting
>  'Invalid Command/ Sequence' error bits which will get set, and start
>  again.

Possibly. We're going to wait and see what Intel say, and then submit a
patch if needed.

Regards,
John Hall

Re: [Fwd: cfi_cmdset_0001.c: do_write_buffer bug]

[David Woodhouse]

John.Hall@optionexist.co.uk said:
>  Possibly. We're going to wait and see what Intel say, and then submit
> a patch if needed.

OK, thanks.

--
dwmw2

RE: [Fwd: cfi_cmdset_0001.c: do_write_buffer bug]

[Joakim Tjernlund]

Hi John

Has Intel responded yet? If yes, do they have a fix?

         Jocke
> 
> 
> On 20 June 2002 13:25 David Woodhouse <dwmw2@infradead.org> wrote:
> 
> > John.Hall@optionexist.co.uk said:
> > >  Not yet. We've spoken to Intel and they acknowledge there might be
> > >  a problem, but we're waiting for them to get back to us.
> 
> > OK, I suspect what we want to do is something like...
> > 
> >  Send WriteToBuffer command.
> >  Poll for a little while for chips to become ready.
> >  If neither chip is ready, repeat.
> >  If only one chip is ready, abort the WriteToBuffer. Send a
> >  zero-length (or one-byte) buffer and then something other than a
> >  WriteConfirm command, to abort the write. Clear the resulting
> >  'Invalid Command/ Sequence' error bits which will get set, and start
> >  again.
> 
> Possibly. We're going to wait and see what Intel say, and then submit a
> patch if needed.
> 
> Regards,
> John Hall
> 
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>