Re: DENALI: can't detect NAND chip

Masahiro Yamada
2018-06-05T01:45:04Z

2018-06-05 7:01 GMT+09:00 Richard Weinberger <richard@sigma-star.at>:
> Am Montag, 4. Juni 2018, 22:57:32 CEST schrieb Richard Weinberger:
>> Am Montag, 4. Juni 2018, 22:51:17 CEST schrieb Boris Brezillon:
>> > > According to the datasheet, the NAND clock rate should be 50Mhz, which is what
>> > > is returned in both cases.
>> > > So this does not really look invalid to me. :)
>> >
>> > Did you try to put a scope on the RE or WE pin? The x2 factor looks too
>> > perfect to be just a coincidence.
>>
>> Not yet, but you are right the x2 factor is really interesting.
>
> The NFC uses two clocks, nand_x_clk and nand_clk.
> nand_clk is nand_x_clk / 4.
> In the device tree nand_clk is referenced, and therefore used to calculate
> the timings. So we might need to use the 200Mhz clock instead of the 50Mhz
> for the calculation.
>

Yes.

Strictly speaking, the Denali IP takes three clocks.

[1] clk : core clock
[2] clk_x: bus interface clock
[3] ecc_clk: for ECC engine

Also in my SoCs (Socionext UniPhier),

clk = 50MHz,
clk_x = ecc_clk = 200MHz

In this case, the ->setup_data_interface hook
is interested in the frequency of [2] clk_x.

However, clk_x is not a core clock.
I admit this is confusing.

If we really want to make the DT-binding precise,
we can change the clock requirement like follows:

clock-names = "clk", "clk_x", "ecc_clk";
clocks = <...>, <...>, <...>;

This might be an annoying churn, though...

--
Best Regards
Masahiro Yamada