From: Cyrille Pitchen <cyrille.pitchen@atmel.com>
To: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com>,
<linux-mtd@lists.infradead.org>
Cc: Marek Vasut <marek.vasut@gmail.com>, Jagan Teki <jagan@openedev.com>
Subject: Re: [PATCH v2] mtd: spi-nor: Add support for N25Q256A13 as N25Q256A
Date: Mon, 30 Jan 2017 14:29:11 +0100 [thread overview]
Message-ID: <23f8030c-272c-1aab-2146-db45dfe77daf@atmel.com> (raw)
In-Reply-To: <1485481897-6368-1-git-send-email-nobuhiro.iwamatsu.kw@hitachi.com>
Hi Nobuhiro,
Le 27/01/2017 à 02:51, Nobuhiro Iwamatsu a écrit :
> Add new Micron N25Q256A (N25Q256A13) 256Mbit NOR Flash in the list
> of supported devices. This chip has the same structure as the N25Q256A
> but ID is different. And this fixes N25Q256A to N25Q256 to fit chip
> name to other n25q chip names.
>
> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com>
> CC: Jagan Teki <jagan@openedev.com>
> CC: Marek Vasut <marek.vasut@gmail.com>
> ---
> drivers/mtd/spi-nor/spi-nor.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index da7cd69d4857..a2a6922e356f 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -887,7 +887,8 @@ static const struct flash_info spi_nor_ids[] = {
> { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
> - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
> + { "n25q256", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
> + { "n25q256a", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
This patch changes the association "n25q256a" <-> 20 ba 19: "n25q256a"
would be now associated to 20 bb 19.
However some device trees use the "micron,n25q256a" as compatible string:
- arch/arm/boot/dts/imx6sx-sbd.dts: compatible = "micron,n25q256a",
"jedec,spi-nor";
- arch/arm/boot/dts/socfpga_arria5_socdk.dts: compatible = "n25q256a";
- arch/arm/boot/dts/socfpga_cyclone5_socrates.dts: compatible = "n25q256a";
- arch/arm/boot/dts/imx6ul-14x14-evk.dts: compatible = "micron,n25q256a";
If the actual JEDEC ID read from the Micron SPI memory of one of these
boards is 20 ba 19 and if you now associate the string "n25q256a" to the
different JEDEC ID 20 bb 19, then spi_nor_scan() is likely to display the
warning message during the boot:
dev_warn(dev, "found %s, expected %s\n", jinfo->name, info->name);
Displaying such a warning during the boot process would be an unwanted side
effect of this patch and users may complain or ask why such warning is now
displayed in the boot log.
You may create a new entry for the 20 bb 19 JEDEC ID but I don't think it
is totally safe to remove the old n25q256a entry.
Best regards,
Cyrille
> { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
> { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>
next prev parent reply other threads:[~2017-01-30 13:29 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-27 1:51 [PATCH v2] mtd: spi-nor: Add support for N25Q256A13 as N25Q256A Nobuhiro Iwamatsu
2017-01-27 4:49 ` Marek Vasut
2017-01-30 13:29 ` Cyrille Pitchen [this message]
2017-01-30 20:38 ` Marek Vasut
2017-01-31 10:18 ` Cyrille Pitchen
2017-02-04 21:32 ` Marek Vasut
2017-02-06 17:53 ` Cyrille Pitchen
2017-02-06 23:09 ` Marek Vasut
2017-01-31 4:51 ` 岩松信洋 / IWAMATSU,NOBUHIRO
2017-01-31 10:32 ` Cyrille Pitchen
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