Re: GPMI iMX6ull timeout on DMA

Christian Eggers
2021-10-13T07:41:22Z

On Saturday, 9 October 2021, 08:26:36 CEST, Christian Eggers wrote:
> > > Do you think that the need for avoiding clock glitches is i.MX6 specific?
> > > The errata I mentioned is specific for the bootloader software, but (I think)
> > > the requirement for switching off the clocks gates prior changing the dividers
> > > may apply also for other series.
> >
> > I honestly don't know, perhaps Han have more details about it. If you
> > think it's a wider issue, then we can just do the disable/enable step
> > without any further checks.
> I also don't know. I can not find the required sequence in the reference manual
> (only in the errata sheet), so I cannot compare with other series. For best
> performance we can start with checking for GPMI_IS_MX6Q(x) and extend it later
> if this issue comes up on other devices.
>
> I sent a question for this on NXP community:
> https://community.nxp.com/t5/i-MX-Processors/ERR007117-Which-i-MX-devices-require-gating-the-clocks-when/m-p/1353018
>
> 1. Which i.MX models / series require this sequence?
> 2. Where can I find this sequence in the reference manuals (e.g. for i.MX6 ULL)?
> 3. How is CCM_CCGR2[CG7] (iomux_ipt_clk_io_clk) related to "gating enfc_clk_root"?

@Han Xu: Can you provide further information about this? Do you have contact to
the hardware developers?

regards
Christian