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[106.168.128.197]) by smtp.gmail.com with ESMTPSA id u14-20020a17090341ce00b0016c20d40ee7sm1055878ple.174.2022.08.12.01.15.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 12 Aug 2022 01:15:16 -0700 (PDT) Message-ID: <283f0672-2596-34c1-bcba-e22edff32898@gmail.com> Date: Fri, 12 Aug 2022 17:15:13 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH 8/8] mtd: spi-nor: spansion: Add support for Infineon Content-Language: en-US From: Takahiro Kuwano To: Tudor.Ambarus@microchip.com, linux-mtd@lists.infradead.org Cc: pratyush@kernel.org, michael@walle.cc, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, Bacem.Daassi@infineon.com, Takahiro.Kuwano@infineon.com References: <80b5e707-23b3-e357-c7ae-f78b6c75f2f6@microchip.com> <4a182200-cff3-94e7-12a3-379638a52560@gmail.com> <43b898eb-cb2a-d905-fba5-cdf707978af7@microchip.com> <6ae143ef-5115-280d-52a2-8081c08bddf7@gmail.com> <7c67ed6d-584f-61fd-a532-b7ff00a6a39f@microchip.com> In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220812_011520_176330_3699F140 X-CRM114-Status: GOOD ( 19.46 ) X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-mtd" Errors-To: linux-mtd-bounces+linux-mtd=archiver.kernel.org@lists.infradead.org Hi Tudor, I submitted another series about address mode discovery. Please review that. I will revise this series after another one is settled. Thanks, Takahiro On 8/8/2022 5:31 PM, Takahiro Kuwano wrote: > On 8/8/2022 5:26 PM, Tudor.Ambarus@microchip.com wrote: >> On 8/8/22 11:09, Takahiro Kuwano wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> On 8/8/2022 4:34 PM, Tudor.Ambarus@microchip.com wrote: >>>> On 8/8/22 09:41, Takahiro Kuwano wrote: >>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>>>> >>>>> On 8/8/2022 3:08 PM, Tudor.Ambarus@microchip.com wrote: >>>>>> On 8/8/22 08:42, Takahiro Kuwano wrote: >>>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>>>>>> >>>>>>> On 8/8/2022 1:47 PM, Tudor.Ambarus@microchip.com wrote: >>>>>>>> On 8/6/22 09:34, tkuw584924@gmail.com wrote: >>>>>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>>>>>>>> >>>>>>>>> From: Takahiro Kuwano >>>>>>>> >>>>>>>> Hi! >>>>>>>> >>>>>>>>> >>>>>>>>> s25hl02gt and s25hs02gt >>>>>>>>> >>>>>>>>> Add ID, flags, and fixup for s25hl02gt and s25hs02gt. >>>>>>>>> These parts are >>>>>>>>> - Dual-die package parts >>>>>>>>> - Not support chip erase >>>>>>>>> - 4-byte addressing mode by default >>>>>>>> >>>>>>>> CFR2N[7] CFR2V[7] says that: "For the DDP or QDP devices, if ADRBYT = 0 >>>>>>>> only the first 128 Mb of die 1 can be accessed." >>>>>>>> So there are flashes of the same family that are by default in 3 byte address >>>>>>>> mode. You added support just for a subset of them and used a generic name, >>>>>>>> which is not accurate, right? >>>>>>>> >>>>>>> We added model #15 (3-byte address mode by default) to address special >>>>>>> requirement from a customer who needs to use bootrom with 3-byte addressing. >>>>>>> Anyway, I overlooked model # difference. Thanks for pointing out this. >>>>>>> >>>>>>>> Can we instead make an algorithm to determine the current address mode? >>>>>>>> >>>>>>> I have just found that we can distinguish model # via BFPT DWORD16. >>>>>>> If Hardware reset, Software reset, or Power cycle can exit 4-byte address >>>>>>> mode, that means the device is 3-byte address mode by default. >>>>>> >>>>>> I don't think this will help us. It doesn't matter the default mode if you >>>>>> have a non volatile register that can be updated and changes the default >>>>>> mode. >>>>>> >>>>>> Are there any registers/data that can be read successively in 3 byte addr mode >>>>>> and then in 4 byte addr mode? We'll then compare what we receive from the flash >>>>>> with a known value and determine the mode. >>>>>> >>>>> As we discussed before [0], if address mode in the controller and device are >>>> >>>> I remember, yes, but without determining the mode, the driver will work only >>>> with flashes that come with the factory settings. The driver will be unusable >>>> if someone changes the address mode in a non volatile way, right? >>>> >>> Yes, right. >>> >>>>> different, the read data will be undetermined. >>>>> >>>>> But if we really want... >>>>> Compare SR1 data read by RDSR1(05h - No Addr) and RDAR(65h - Addr 0). >>>>> In most cases (without block protection), SR1=00h. The value of 00h would be >>>>> awkward to determine if this is 'real' output from Flash or not. So, use> WREN(06h) and WRDI(04h) that flips BIT(1) in SR1. >>>> >>>> Would be good to have more fixed/OPT-like bits, or if we could change more bits >>>> to increase the chances to not hit just some undetermined data. >>>>> >>>>> Therefore, something like: >>>>> 1) RDSR1 >>>>> 2) RDAR with 3-byte addr (000000h) >>>>> 3) If #1 == #2 >>>>> 4) WREN >>>>> 5) RDAR with 3-byte addr (000000h) >>>>> 6) BIT(1) is SR1==1? >>>>> ... >>>>> >>>>> Or simply WREN -> RDAR -> WRDI -> RDAR then check if only BIT(1) is toggled. >>>> >>>> Both may work, yes, but making the assumption on only one bit is fragile. >>>> Can we use the Read Any Register Command with 3 and 4 byte address modes and >>>> compare the values? Are there any registers with fixed values? >>>> >>> Register values can vary because it's register:) >>> >>> So... let's use Data Integrity Check CRC registers. These registers do not >>> have fixed values but we can calculate expected values by offline. Read >>> several bytes (>=4) from Flash array with Read(03h) then calculate CRC by >>> crc32(). Issue Data integrity Check command (5Bh) followed by start and >>> end address (4-byte for each), wait till ready. Read calculated CRC by >>> Read Any Register in 3 and 4 byte address (00800095h~0080098h) then compare >>> the crc32() result and register read result. >> >> Much better, yes. I think it is worth it. What's your opinion, Takahiro? >> Others, Michael, Pratyush? >> > OK, I will prototype and test it. ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/