Data Reliability

Data Reliability

[Bob Canup]

Is Vipin correct that there is a problem if there is a power loss when
writing to flash in embedded systems? Yes, no question.

There are 2 main ways of handling any problem. 1. Fix the problem once
it occurs. 2. Avoid the problem in the first place.

I have already given two ways to avoid the problem: use the flash in
Read Only mode, or have a power supply which signals impending power
loss and holds itself up long enough to allow an ordered shut down.

It has been my experience that it is generally better to avoid problems
than to attempt to fix them after they have occurred. Sometimes this is
not possible. For example: hard drives have to have ECC built into them
because it is virtually impossible to keep from having read errors.

I don't see any practical ways of fixing the problem of trashed flash
chips once it occurs. Does anyone else have any other suggestions as to
how to either avoid the problem or fix it once it happens?




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RE: Data Reliability

[Bjorn Eriksson]

>I have already given two ways to avoid the problem: use the flash in
>Read Only mode, or have a power supply which signals impending power
>loss and holds itself up long enough to allow an ordered shut down.

Definitely my choice. Anyone else working on this?


//Björnen.




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RE: Data Reliability

[Kira Brown]

On Tue, 7 Dec 1999, Bjorn Eriksson wrote:

> >I have already given two ways to avoid the problem: use the flash in
> >Read Only mode, or have a power supply which signals impending power
> >loss and holds itself up long enough to allow an ordered shut down.
> 
> Definitely my choice. Anyone else working on this?

We've already done it.  Since we have not a lot running on the system, a
shutdown -h takes less than a third of a second on a 99MHz AMD Elan SC410
driving an 8Mbyte DoC2000.  We didn't write any special code other than a
little thingy (technical term) that watches one of the processor GPIO pins
for a falling edge and executes a shutdown if it sees one.  One of those
funky 1F memory retention caps provides the power to do this.  (Do those
things scare anyone else or is it just me?)

kira.



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RE: Data Reliability

[Bjorn Eriksson]

>We've already done it.  Since we have not a lot running on the system, a
>shutdown -h takes less than a third of a second on a 99MHz AMD Elan SC410
>driving an 8Mbyte DoC2000.  We didn't write any special code other than a
>little thingy (technical term) that watches one of the processor GPIO pins
>for a falling edge and executes a shutdown if it sees one.  One of those
>funky 1F memory retention caps provides the power to do this.  (Do those
>things scare anyone else or is it just me?)

 Uhm, do you let your SC410 keep cruising at 99MHz? ISTR that these "funky 
memory retention caps" (FMRC:) holds up kinda bad under heavy load. I've 
got myself a seriously funky MRC that's either 3F or 700uF depending on how 
heavy a load I've got at the point of power failure.

P.s Do you know any venues for SC4xx designs/info/refs? Considering how 
many people are designing with this beast there preciously little noise on 
the Web. Right now I'm fighting GPCSA who stubbornly asserts his right to 
drive *ALL* the GPIO_CS's :-) D.s


//Björn Eriksson



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RE: Data Reliability

[Kira Brown]

On Tue, 21 Dec 1999, Bjorn Eriksson wrote:
> 
>  Uhm, do you let your SC410 keep cruising at 99MHz?

Nope; I have a little program that bumps it down to 8MHz as soon as
powerfail is detected.

> ISTR that these "funky memory retention caps" (FMRC:) holds up kinda
> bad under heavy load.

Yes.  But well enough, we find.

> P.s Do you know any venues for SC4xx designs/info/refs? Considering how 

I'd have to ask David (our hardware designer).  He knows this thing inside
and out.

> many people are designing with this beast there preciously little noise on 
> the Web. Right now I'm fighting GPCSA who stubbornly asserts his right to 
> drive *ALL* the GPIO_CS's

Ooooh, that's *good*.  We just bite the bullet and build more hardware
when we need that sort of thing...

kira.



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