Compile problems

Compile problems

[Jason Gunthorpe]

Hi all,

Just been working on getting the latest MTD cvs to compile on
2.3.99-pre8-rmk2 for an ARM platform.

There are a few issues it seems, someone should decide what they mean, I 
suppose..

1) Damn Odd compile errors

mtdcore.c:350: warning: `init_mtd' defined but not used
mtdcore.c:374: warning: `cleanup_mtd' defined but not used
{standard input}: Assembler messages:
{standard input}:6: Warning: Ignoring changed section attributes for
.modinfo

The first two are due to the init/cleanup functions being declared static.
The second two are due to gcc emitting some very odd assembly:

@ Generated by gcc 2.95.2 19991024 (release) for ARM/elf
        .file   "mtdcore.c"
gcc2_compiled.:
        .section .modinfo
        .previous
.section        .modinfo,"a",%progbits
        .align  2
        .type    __module_kernel_version,object
        .size    __module_kernel_version,32
__module_kernel_version:
        .ascii  "kernel_version=2.3.99-pre8-rmk2\000"
.section        .rodata
[...]

The '.section .modinfo\n.previous' comes from the kernel module.h header,
the second section declaration directly after comes from GCC.. I don't
recall seeing this when compiling the kernel proper, so maybe there is
something strange about the MTD stuff?

2) ioremap, memcpy_fromio, etc seem to be PCI things

Most of the low level drivers won't even compile, mostly because my ARM
arch doesn't have PCI or ISA io functions :> But reading around I think
the slram,vmax and oct drivers are wrong.. vmax and oct should
probably use the isa_* flavors of all the functions, and I don't know how
slram should try to portably access the end of memory, but ioremap
probably isn't it? 

Jason



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Re: Compile problems

[David Woodhouse]

On Sat, 24 Jun 2000, Jason Gunthorpe wrote:

> Just been working on getting the latest MTD cvs to compile on
> 2.3.99-pre8-rmk2 for an ARM platform.

I've tested it on 2.4/ia32 and 2.2/ARM. Not yet 2.4/ARM although I didn't
expect it to break.


> 1) Damn Odd compile errors
> 
> mtdcore.c:350: warning: `init_mtd' defined but not used
> mtdcore.c:374: warning: `cleanup_mtd' defined but not used
> {standard input}: Assembler messages:
> {standard input}:6: Warning: Ignoring changed section attributes for
> .modinfo
> 
> The first two are due to the init/cleanup functions being declared static.

That's known and harmless. They're not unused; they're aliased. Consider
it a GCC bug and ignore it.

> The second two are due to gcc emitting some very odd assembly:
	<snip>
> 
> The '.section .modinfo\n.previous' comes from the kernel module.h header,
> the second section declaration directly after comes from GCC.. I don't
> recall seeing this when compiling the kernel proper, so maybe there is
> something strange about the MTD stuff?

Not knowingly. Prod rmk or a gcc hacker. Also try cutting out stuff till
it goes away and work out exactly what's causing it. Do you have MTD_DEBUG
defined?

> 2) ioremap, memcpy_fromio, etc seem to be PCI things
> 
> Most of the low level drivers won't even compile, mostly because my ARM
> arch doesn't have PCI or ISA io functions :> 

Ah - on mine they're defined to panic()

> But reading around I think the slram,vmax and oct drivers are wrong..
> vmax and oct should probably use the isa_* flavors of all the
> functions, and I don't know how slram should try to portably access
> the end of memory, but ioremap probably isn't it?

Yes, vmax and oct should use the isa_ functions. Also, they should only be
configurable if CONFIG_ISA is set, if they're ISA boards.

slram I haven't looked at for a while, and I'm not sure what to do with it
either. 

To get the DiskOnChip drivers to work, just stick #ifndef __arm__ around:

#define ReadDOC(adr, reg)      readb(((unsigned long)adr) + DoC_##reg)
#define WriteDOC(d, adr, reg)  writeb(d, ((unsigned long)adr) + DoC_##reg)

... in include/linux/mtd/doc2000.h and #else the appropriate alternative.
Also ifdef the ioremap in docprobe.c and the iounmap in docprobe.c and
doc200[01].c


-- 
dwmw2




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Re: Compile problems

[Jason Gunthorpe]

On Sun, 25 Jun 2000, David Woodhouse wrote:

> > Just been working on getting the latest MTD cvs to compile on
> > 2.3.99-pre8-rmk2 for an ARM platform.
 
> I've tested it on 2.4/ia32 and 2.2/ARM. Not yet 2.4/ARM although I didn't
> expect it to break.

Well, I am also using a very odd arm sub-arch (cl-ps7500fe)

> > The first two are due to the init/cleanup functions being declared static.
> 
> That's known and harmless. They're not unused; they're aliased. Consider
> it a GCC bug and ignore it.

Thats what I thought.. I wonder has anyone told the GCC people?
 
> > The '.section .modinfo\n.previous' comes from the kernel module.h header,
> > the second section declaration directly after comes from GCC.. I don't
> > recall seeing this when compiling the kernel proper, so maybe there is
> > something strange about the MTD stuff?
> 
> Not knowingly. Prod rmk or a gcc hacker. Also try cutting out stuff till
> it goes away and work out exactly what's causing it. Do you have MTD_DEBUG
> defined?

No, I don't think I do. I'll ask on the ARM list later then..
 
> > 2) ioremap, memcpy_fromio, etc seem to be PCI things
> > 
> > Most of the low level drivers won't even compile, mostly because my ARM
> > arch doesn't have PCI or ISA io functions :> 
> 
> Ah - on mine they're defined to panic()

Heh, on my arch they just aren't defined :| Thats OK, I shouldn't be
compiling most of those drivers as they are i386 only (particularly the
SBC drivers)
 
> Yes, vmax and oct should use the isa_ functions. Also, they should only be
> configurable if CONFIG_ISA is set, if they're ISA boards.

Well, they are SBCS, so they should be available if CONFIG_ISA and
whatever the I386 test is set.
 
> To get the DiskOnChip drivers to work, just stick #ifndef __arm__ around:
> 
> #define ReadDOC(adr, reg)      readb(((unsigned long)adr) + DoC_##reg)
> #define WriteDOC(d, adr, reg)  writeb(d, ((unsigned long)adr) + DoC_##reg)
> 
> ... in include/linux/mtd/doc2000.h and #else the appropriate alternative.
> Also ifdef the ioremap in docprobe.c and the iounmap in docprobe.c and
> doc200[01].c

Having not looked at it, shouldn't the DOC access be regulated to a lower
level driver, like we have for the other flash stuff? If I were to slap a
DOC on an ARM board here it would probably have quite different access (32
bit for one thing). 

BTW, I am almost finished redoing my JEDEC stuff to be more like your CFI
stuff [turns out my SIMM was made in 1995, no CFI] and adding support for
interleved and banked memories.. will send you a patch soon. 

I did add two new things to the struct map to make this possible:

  unsigned bus_width;    // Number of data bits between host<->memregion
  unsigned long bank_size;   // Bytes in a bank. size = bank_size*bank_count

Both should always be settable by a low level driver, they are determined
by the eletrical connections of the device. bus_width is 8/16/32 and
bank_size is to basically support FLASH SIMMS which have 4 chip select
lines E[0-4] that select 1 of 4 banks of chips. It is expected that these
lines will be driven by the host at some specific address interval, mine
is 4Meg. So if you have less than 4 meg of chips you end up with spaces
between them and the driver has to advoid them and probe differently. 

Jason



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Re: Compile problems

[David Woodhouse]

jgg@deltatee.com said:
>  Having not looked at it, shouldn't the DOC access be regulated to a
> lower level driver, like we have for the other flash stuff? If I were
> to slap a DOC on an ARM board here it would probably have quite
> different access (32 bit for one thing).  

Urgh. You might be right. Which is a shame because the current map setup 
doesn't handle the type of access that the DiskOnChip requires very nicely. 
Where it's reading 512 consecutive bytes out of the same port on the ASIC, 
it'd be 512 indirect function calls in a tight loop. Maybe we need an extra 
method in the map object if we're going to do that.

Lets try to avoid it for a while - presumably anyone who adds a DiskOnChip 
to an ARM system will do the same thing, so the ReadDOC and WriteDOC macros 
can be defined accordingly for ARM systems, and we'll bury our head in the 
sand for a little longer until some nutter comes up with a second method 
for a given architecture and we can no longer ifdef it. :)


jgg@deltatee.com said:
> I did add two new things to the struct map to make this possible:
>   unsigned bus_width;

Good point.

>   unsigned long bank_size;   // Bytes in a bank. size = bank_size*bank_count 

> So if you have less than 4 meg of chips you end up with spaces between
> them and the driver has to advoid them and probe differently.  

I have the same - 16Mb at 0x0, 16Mb at 0x2000000. But it's aliases, not 
spaces between them - just to make it more interesting. (And I was told it 
wouldn't be like that, so when I erased the 'second' chip at 0x1000000 I 
was actually erasing the firmware... :) 

I changed the VM setup to present them to the CPU contiguously. If that wasn't
possible, I'd have done the mask-and-shift necessary in the map driver. Is
it really necessary for the user to know about it? Surely it's just a
physical detail of the wiring?




--
dwmw2




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Re: Compile problems

[David Woodhouse]

jgg@deltatee.com said:
>  BTW, I am almost finished redoing my JEDEC stuff to be more like your
> CFI stuff [turns out my SIMM was made in 1995, no CFI] and adding
> support for interleved and banked memories.. will send you a patch
> soon. 

Like my CFI stuff will be when I've finished it, I assume - not like it is 
at the moment - busy waiting and only detecting one chip in a mapping :)

I'm going to protect each chip with its own spinlock, and make erases 
asynchronous. I was hoping to do that last week, but it doesn't seem to 
have happened. Maybe this week.

--
dwmw2




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Re: Compile problems

[Jason Gunthorpe]

On Mon, 26 Jun 2000, David Woodhouse wrote:

> Lets try to avoid it for a while - presumably anyone who adds a DiskOnChip 
> to an ARM system will do the same thing, so the ReadDOC and WriteDOC macros 
> can be defined accordingly for ARM systems, and we'll bury our head in the 
> sand for a little longer until some nutter comes up with a second method 
> for a given architecture and we can no longer ifdef it. :)

Okay, I'm not sure how popular DOC will be long term, thought their new
parts look kind of nice.. (small physical size and all)

> >   unsigned long bank_size;   // Bytes in a bank. size = bank_size*bank_count 

> > So if you have less than 4 meg of chips you end up with spaces between
> > them and the driver has to advoid them and probe differently.  
> 
> I have the same - 16Mb at 0x0, 16Mb at 0x2000000. But it's aliases, not 
> spaces between them - just to make it more interesting. (And I was told it 
> wouldn't be like that, so when I erased the 'second' chip at 0x1000000 I 
> was actually erasing the firmware... :) 

Yes, aliases is what it always should be, in fact my driver counts on it
:> How it works is they just connect up the necessary address lines and
use the E[0-4] lines as chip selects. Chip selects are generated by a PLD.
I expect more elaborate systems will have a PLD that has configurable bank
size..

Usually I think that anything that is not perfectly linear is either that
way because someone is abusing CPU CS lines, or because they expect to
have the option to install larger chips in future.

> I changed the VM setup to present them to the CPU contiguously. If that wasn't
> possible, I'd have done the mask-and-shift necessary in the map driver. Is

That is only possible if you know the chip size in advance, or are willing
to add APIs to dynamically remap this stuff. I have here a socket, you can
plug whatever you want into it. If that happens to be anything less than a
32 meg part you end up with holes. Plus, on my ARM board the mapping of
the flash is done on boot, I'm not sure it can be remapped..

Fortunately it turns out to be not too much code to worry about.

> it really necessary for the user to know about it? Surely it's just a
> physical detail of the wiring?

If the mapping driver knows the chip size in advance it can remap as you
have done and set that value to the mapping size, otherwise I think it is
necessary to have support in a higher layer. It is definately required for
detection, and is only a minor amount of code for
writing/eraseing/reading. For reading I made a seperate function for
speed, the other functions are already so slow nobody will notice :>

Ideally, if the mapping driver can remap then after the detection sequence
it would remap it as necessary and re-detect to get a linear view. Some
drivers (such as windowed ones, maybe this ARM one too) can't remap even
if they wanted to.

Jason



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Re: Compile problems

[Jason Gunthorpe]

On Mon, 26 Jun 2000, David Woodhouse wrote:

> Like my CFI stuff will be when I've finished it, I assume - not like it is 
> at the moment - busy waiting and only detecting one chip in a mapping :)

Hopefully close :> I have the whole thing done, just need to test it now.
 
> I'm going to protect each chip with its own spinlock, and make erases 
> asynchronous. I was hoping to do that last week, but it doesn't seem to 
> have happened. Maybe this week.

If you do that can you do the JEDEC one too? I'm not at all sure how
to ho about doing that, but the flash_erase function is split just so
someone eventually could. 

Seperate spinlocks is possible too, each chip has it's own little struct
that can be locked off.

Jason



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RE: Problems with AMD CFI chips

[mark.langsdorf]

> mark.langsdorf@amd.com said:
> >  The Flash bank is found correctly, and loads, and I can 
> > write to it.
> > However, when I boot from it, I can't seem to get it to 
> > commit writes- either creating new files or altering old
> > ones.  Once I reboot the device, my changes are gone.
> 
> Please check using the /dev/mtd0 device directly to see 
> whether your writes are 'taking'. 

	I can write to /dev/mtd0, the writes through the char
interface are definitely consistent over power-outs.  It's
only when I use jffs on /dev/mtdblock0 that I run into problems.

> What 'map' driver are you using?

	Modified version of physmap, since the flash banks are
physically mapped at 0x2000000 but I needed to partition them
because the BIOS and kernel image are also stored on the same
banks.

> for me on the iPAQ because I wasn't enabling the Vpp voltage
> during write cycles. Is this necessary on your targer?
> 
> Other than that, poke the author and/or look at the code 
> yourself to see what's happening. What interleave/buswidth
> are you using?

	Interleave 2, 4 byte buswidth, to support 2 16 bit chips.
Again, that all looks pretty consistent.

	I think it may be some kind of interaction with jffs,
because I've had limited success with creating directories 
and deleting files, but not consistently.  I'm not sure where
I should look in the jffs code to get more information, though,
and would appreciate some pointers.
	Also, when does jffs attempt to clean out the dirty
space?  thread_should_wake reports upwards of 2 megs of
dirty space, which is about 16 sectors and 14% of the available
memory.  I'd think that should get returned to the free list
much earlier, especially during the reboots.

-Mark Langsdorf
AMD, Inc.


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Re: Problems with AMD CFI chips

[Gregory Schallert]

>    Also, when does jffs attempt to clean out the dirty
> space?

On an aside, how does jffs schedule the clean up and is this really CPU
intensive?



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RE: Problems with AMD CFI chips

[David Woodhouse]

On Thu, 2 Nov 2000 mark.langsdorf@amd.com wrote:

> 	Interleave 2, 4 byte buswidth, to support 2 16 bit chips.
> Again, that all looks pretty consistent.

Should be fine. ISTR that's what the original author was using.

> 	I think it may be some kind of interaction with jffs,
> because I've had limited success with creating directories 
> and deleting files, but not consistently.  I'm not sure where
> I should look in the jffs code to get more information, though,
> and would appreciate some pointers.

Make sure you've got up-to-date JFFS code. Or the code in the 2.4 kernel
is known good.

Hack flash_safe_write() to read back the data afterwards and verify it.

> 	Also, when does jffs attempt to clean out the dirty
> space?  thread_should_wake reports upwards of 2 megs of
> dirty space, which is about 16 sectors and 14% of the available
> memory.  I'd think that should get returned to the free list
> much earlier, especially during the reboots.

When the free space goes below gc_minfree_threshold or the dirty space
goes above gc_maxdirty_threshold. These are defined as 5% and 33% of the
total size of the flash partition, respectively. 

It's inefficient to GC too much before it's needed. In an ideal world,
we'd always have just enough free space to handle the next write without
having to wait for GC to happen.

-- 
dwmw2




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Re: Problems with AMD CFI chips

[David Woodhouse]

On Thu, 2 Nov 2000, Gregory Schallert wrote:

> On an aside, how does jffs schedule the clean up and is this really CPU
> intensive?

While the conditions I quoted before are met, the jffs_gcd kernel thread
wakes up and does it in the background.

If the GC thread is ever killed by the user, or for some reason it's
been really slow and we've actually run out of free space, GC can also be
done from the user's context, to make room for a write to happen.

-- 
dwmw2




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Compile problems

[Gregory Schallert]

I am having a couple of problem compelling I think that it is fixed with
a patch.  I was wondering what is the syntax for applying the .patch
files?



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Re: Compile problems

[David Woodhouse]

On Fri, 3 Nov 2000, Gregory Schallert wrote:

> I am having a couple of problem compelling I think that it is fixed with
> a patch.  I was wondering what is the syntax for applying the .patch
> files?

Something like 'patch -p0 < patchfile'

-- 
dwmw2




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