Re: Different nand interface

[Alice Hennessy <ahennessy@mvista.com>]

David Woodhouse wrote:

> On Mon, 2003-10-27 at 10:25 -0800, Alice Hennessy wrote (modulo newlines):
> > Yes, I am looking at the current code which is more modular so it
> > gives me hope.
> > There are 2 nand chips on the board.  If you want to read from the
> > 0x100th byte on chip 1 you need to do readb(chip1_base + 0x100);  if
> > you want to write the 0x10000th byte on chip 2 you need to do
> > writeb(chip2_base + 0x10000,bytedata).
> > The chips are 16M X 8 bit and  are mapped in a contiguous 32 M byte
> > memory space with 0-16M for chip1 and 16-32M for chip2.
>
> That's weird. How are the out-of-band areas accessed? How do you send
> commands like READ_ID and ERASE?
>
> --
> dwmw2

The hardware logic uses register access for special commands.   Readid,
status does
2 writes to a register, one for address (to distinquish which flash), one for
command and one more
to read.  Erase takes 2 writes to a register, address then command.   The
out-of-band access
uses a register to give a command and then the out-of-band data is read using

readb with  offset.

Alice