Re: DQ7 vs DQ6 in flash erase/write

[David Vrabel <dvrabel@arcom.com>]

Hi,

> On Am29LV256M with the same board, the chip is writable but not erasable.

I have this part and it works.  I suspect a board specific issue.

> After long time investigation on the problem I found the following comment
> on ver 1.3 of cfi_cmdset_0002.c.

1.3?  That's fossilized.

> 
>    /* The dq6 toggling method of determining whether the erase is finished
>     * doesn't seem to work for the Fujistu flash chips populated on the
>     * TQM8260 board. We poll dq7 instead.
>     */

This sounds like a problem with a particular Fujitsu chip.  It would 
have been helpful for the person writing that comment to have mentioned 
which chip had the problem.

> 2. Why was the data polling algorithm (DQ7) removed?

Earlier versions were a mess with code for reading the chip status all 
over the place.  I refactored it for easier maintainance.

> 3. Will polling DQ7 be supported later?

If someone implements it in a clean way I don't see why not.

A quick look at the AM29PL320 datasheet indicates that the chip supports 
the DQ6 toggle algorithm.  I'm leaning towards a board specific issue 
unless you have information from AMD regarding non-functionality of the 
toggle-bit algorithm on this chip?

Are the chips interleaved?  I've never tested interleaving so that may 
be broken.

Other than that all I can suggest is that maybe something other than the 
MTD driver is accessing the flash.  This would certainly mess up the 
toggle bit algorithm.  Perhaps the chip selects are setup incorrectly?

David Vrabel
-- 
David Vrabel, Design Engineer

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