Re: Large block NAND

[David Updegraff <dave@cray.com>]

Does anyone know how 'industry-standard' the format of the 4th ID byte 
in these large NAND chips from Samsung is?  Y'know, the one that tells 
you pagesize, buswidth, etc.  I'd sure be sweet to be able to reliably 
use them.


>> > I'm going to write a driver for the Samsung Flash K9F1G08U0M (128MB).
>> > The main characteristics are:
>> > - erase block size: 128 KB
>> > - page program size: 2 KB
>> > - total chip size: 128 MB
>> > - tR = 25 us
>> >
>> > This chip is not fully compatible with the standard NAND flash commands
>> > defined in
>> > nand.h (Samsung call these devices "large block").
>> > Thus, in my understanding, I must provide the following custom 
>> functions:
>> > my_board_nand_command
>> > my_board_nand_wait
>> > my_board_nand_block_bad
>>
>> Those functions should be incorporated into nand.c, as they are 
>> generic. So
>> all boards which use those "large block" devices can use them.
>>
>> Be aware, that the available NAND aware filesystems must be changed 
>> too, as
>> they are not aware of pagesizes > 512 byte, but if IIRC  the datasheet
>> details it is possible to write 4  512 byte sub-pages to the device 
>> without
>> violating the specs. Anyway changes will be neccecary.
> 
> 
> I see.
> 
>> > Anybody wrote a driver for a similar device?
>> > Have the MTD maintainers already planned to support these devices?
>>
>> Yep, but nobody forced me / us to implement it by paying for it. :)
> 
> 
> In case we decide to implement this feature by ourselves:
> 1) will the code be included in the public CVS tree?
> 2) will we guided by you and David in order to write the code the right 
> way (I
> mean, for example, using the correct notations and coding style)?
> 
> 
> 
> Regards,
> 
> llandre
> 
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