[patch] cfi: remove warning message on expected behaivor

[patch] cfi: remove warning message on expected behaivor

[Jan Pedersen]

When an erase operation is in progress, the DQ5 (data bit 5 / exceeded
timing limit) pin on the flash chips may raise just before operation
complete is detected. This is expected behaivor because when the erase is
complete, DQ5 switches from 'exceeded timing limit' to 'data bit 5' which
therefore might be read as '1' just before operation complete is detected.
This fix is well tested.

Signed-off-by: Jan Pedersen <jp@jp-embedded.com>
---
diff -Naur linux-2.4.31.org/drivers/mtd/chips/cfi_cmdset_0002.c
linux-2.4.31/drivers/mtd/chips/cfi_cmdset_0002.c
--- linux-2.4.31.org/drivers/mtd/chips/cfi_cmdset_0002.c	2004-11-17
06:54:21.000000000 -0500
+++ linux-2.4.31/drivers/mtd/chips/cfi_cmdset_0002.c	2005-08-22
12:14:17.000000000 -0400
@@ -950,12 +950,8 @@
 		    oldstatus   = cfi_read( map, adr );
 		    status      = cfi_read( map, adr );
 		    
-		    if( ( oldstatus & 0x00FF ) == ( status & 0x00FF ) )
+		    if( ( oldstatus & 0x00FF ) != ( status & 0x00FF ) )
 		    {
-                printk( "Warning: DQ5 raised while erase operation was in
progress, but erase completed OK\n" ); 		    
-		    } 			
-			else
-            {
 			    /* DQ5 is active so we can do a reset and stop
the erase */
 				cfi_write(map, CMD(0xF0), chip->start);
                 printk( KERN_WARNING "Internal flash device timeout occured
or write operation was performed while flash was erasing\n" );

Re: [patch] cfi: remove warning message on expected behaivor

[Jörn Engel]

On Tue, 4 October 2005 22:49:21 +0200, Jan Pedersen wrote:
> 
> When an erase operation is in progress, the DQ5 (data bit 5 / exceeded
> timing limit) pin on the flash chips may raise just before operation
> complete is detected. This is expected behaivor because when the erase is
> complete, DQ5 switches from 'exceeded timing limit' to 'data bit 5' which
> therefore might be read as '1' just before operation complete is detected.
> This fix is well tested.

Do you have a testcase that fails with old code and succeeds with new
code?

> Signed-off-by: Jan Pedersen <jp@jp-embedded.com>
> ---
> diff -Naur linux-2.4.31.org/drivers/mtd/chips/cfi_cmdset_0002.c
> linux-2.4.31/drivers/mtd/chips/cfi_cmdset_0002.c
> --- linux-2.4.31.org/drivers/mtd/chips/cfi_cmdset_0002.c	2004-11-17
> 06:54:21.000000000 -0500
> +++ linux-2.4.31/drivers/mtd/chips/cfi_cmdset_0002.c	2005-08-22
> 12:14:17.000000000 -0400
> @@ -950,12 +950,8 @@
>  		    oldstatus   = cfi_read( map, adr );
>  		    status      = cfi_read( map, adr );
>  		    
> -		    if( ( oldstatus & 0x00FF ) == ( status & 0x00FF ) )
> +		    if( ( oldstatus & 0x00FF ) != ( status & 0x00FF ) )
>  		    {
> -                printk( "Warning: DQ5 raised while erase operation was in
> progress, but erase completed OK\n" ); 		    
> -		    } 			
> -			else
> -            {
>  			    /* DQ5 is active so we can do a reset and stop
> the erase */
>  				cfi_write(map, CMD(0xF0), chip->start);
>                  printk( KERN_WARNING "Internal flash device timeout occured
> or write operation was performed while flash was erasing\n" );

Jörn

-- 
The grand essentials of happiness are: something to do, something to
love, and something to hope for.
-- Allan K. Chalmers

Re: [patch] cfi: remove warning message on expected behaivor

[David Vrabel]

Jan Pedersen wrote:
> When an erase operation is in progress, the DQ5 (data bit 5 / exceeded
> timing limit) pin on the flash chips may raise just before operation
> complete is detected. This is expected behaivor because when the erase is
> complete, DQ5 switches from 'exceeded timing limit' to 'data bit 5' which
> therefore might be read as '1' just before operation complete is detected.
> This fix is well tested.

If you look at the current cfi_cmdset_0002.c (in 2.6) you'll notice that
all it does it check for toggling bits.  The software timeout handles
failed erases and writes rather than checking DQ5.

Trying to handle the various error bits was deemed too tricky/complex to
get right for interleaved chips.

David Vrabel
-- 
David Vrabel, Design Engineer

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