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Date: Tue, 06 Dec 2005 13:14:34 +0100
From: Bernhard Priewasser <priewasser@gmail.com>
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Subject: Re: Strange NOR read/write throughput behaviour
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> Sorry for the long wait.
No problem.

> Let me ask around a little more.  This is an arm7 processor,
> no L1 or L2 caches?
ARM 720T, 8 KiB combined instruction/data cache. I don't know if there 
is any L2-Cache on Hynix HMS30C7202; but if there is one, I doubt it's 
as big as 128 KiB.
It looks pretty much like there is a cache sized 128 KiB somewhere 
beetween fread() and the flash. But don't know where...

-- 
Bernhard